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freescale semiconductor engineering bulletin EB632 rev. 2, 1/2005 ? freescale semiconductor, inc., 2002, 2005. all rights reserved. 1 introduction this document describes the differences between msc8101 mask set 2k42a and msc8103 mask set 2k87m. these differences include: ? system interface unit (siu) changes: ? internal memory map register (immr) masknum field value ? addition of the internal memory map mirror register (immmr) reset changes: ? modes ? hard reset configuration word (hrcw) layout boot source changes clock changes ? clock scheme ? system clock mode register (scmr) ? addition of the clkodis field to the system clock control register (sccr) ? clock modes ? clkin to clkout delay change ? maximum clock frequencies change memory map addition of immmr orx in upm mode, bit 27 functionality difference host interface (hdi16) changes direct memory access (dma) controller transfer code (tc) definitions contents 1 introduction.........................................................1 2 summary of differences .....................................2 3 siu ......................................................................3 4 reset....................................................................6 5 boot.....................................................................9 6 clock system ....................................................14 7 memory map ....................................................22 8 orx in upm mode...........................................22 9 hdi16 ...............................................................22 10 dma transfer code definitions ......................36 11 interrupt system................................................36 12 debugging.........................................................36 13 efcop ..............................................................37 14 cpm ..................................................................37 15 errata.................................................................56 a bootloader program ..........................................82 functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m)
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 2 freescale semiconductor summary of differences interrupt system changes: ? cpm low interrupt priority registers (scprr_l and scprr_l_ext) definitions ? assignment of interrupt vector 44 to transmission convergence (tc) layer request debugging system changes: ? jtag id ? eonce status register (esr) values removal of enhanced filter coprocessor (efcop) support communications processor module (cpm) changes: ? risc controller configuration register (rccr) ? dual-port ram ? addition of rom-based inverse multiplexing for atm (ima) microcode ? addition of tc layer functionality to the time-slot assigner (tsa) with support through fcc2 ? addition of new mcc host commands errata new bootloader program 2 summary of differences ta bl e 1 lists a summary of the differences between msc8101 mask set 2k42a and msc8103 mask set 2k87m. table 1. difference summary for msc8101 mask set 2k42a and msc8103 mask set 2k87m module function msc8101 mask set 2k42a msc8103 mask set 2k87m system interface unit (siu) internal memory map register (immr) masknum bit field = 0x02 masknum bit field = 0x12 internal memory map mirror register (immmr) not supported added reset supported modes host reset and hardware reset host reset, hardware reset, and reduced reset hardware reset configuration word seventeen fields defined eighteen fields defined--software watchdog disable (swdis) bit added boot boot sources supported from host (hdi16) or external memory (system bus) from host (hdi16), external memory (system bus), or serial eprom (i 2 c interface) clock clock scheme clock scheme configures spll pdf, spll mf, and bus df clock scheme configures spll pdf, spll mf, bus df, cpm df, core df, cpll pdf, and cpll mf system clock mode register (scmr) defines seven fields defines eight fields system clock control register (sccr) defines one field (dfbrg) defines two fields (clkodis and dfbrg) clock modes two valid modes twenty-seven valid modes clkin-to-clkout delay a function of frequency not a function of frequency enabling the dll dll-enabled mode is not supported and designs must use a zero-delay clock buffer. to enable the dll, the zero-delay clock buffer recommended for the 2k42a mask set must be placed in pll-bypass mode or replaced. disabling the dll ? for clock modes 5, 6, 46, and 57, apply offsets to dll-disabled timing. maximum clock frequencies bclk/clkout/sclk = 68.75 mhz cpmclk = 137.5 mhz dspclk = 275 mhz bclk/clkout/sclk = 100 mhz cpmclk = 200 mhz dspclk = 300 mhz
siu functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 3 3siu 3.1 internal memory map register (immr) change the immr is updated in 2k87m to reflect the mask change. the masknum bit field has changed to 0x12 to reflect the correct revision level. memory map immmr not supported added sccr not supported added memory controller orx in upm mode bit 27 is a wait state bit. when bit 27 is set, it add one wait state to the memory cycle. bit 27 is reserved. host port (hdi16) icr and isr icr and isr do not support hdi6 bursts of different sizes icr and isr redefined to support hdi16 burst of several sizes. direct memory access (dma) controller transfer code (tc) bit definitions as defined in table 31 of this document. the transfer code (tc) bit definitions are modified to conform to the original specification as listed in ta ble 31 of this document. interrupts scprr_l and scprr_l_ext yc1p?yc8p field definitions the value 100 is reserved. the value 100 = ?tc layer asserts its request in the yccn position.? interrupt vector 44 reserved assigned to tc layer interrupt. jtag/ eonce system jtag id 0x0188101d 0x1188101d eonce status register (esr) values esr[revno] = 1 esr[coretp] = 0 esr[revno] = 2 esr[coretp] = 2 efcop enhanced filter coprocessor supported as defined in the msc8101 reference manual not supported cpm risc controller configuration register (rccr) enable ram microcode (eram) field 3 bits wide enable ram microcode (eram) field changed to 4 bits wide dual-port ram 24 kb 32 kb ima functionality not available added serial interface (si) and time-slot assigner (tsa) no tsa layer functionality. tc layer functionality added to the tsa for atm with a new interrupt (vector 44) all errata documented in the current errata list see table 48 , table 49 , and table 50 for details. bootloader program code list available upon request. listed in appendix a table 1. difference summary for msc8101 mask set 2k42a and msc8103 mask set 2k87m (continued) module function msc8101 mask set 2k42a msc8103 mask set 2k87m
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 4 freescale semiconductor siu 3.1.1 2k42a mask set immr values immr identifies a specific device as well as the base address for the internal memory map. software can deduce availability and location of any on-chip system resources from the values in immr. partnum and masknum are mask programmed and cannot be changed for any particular device. immr internal memory map register 0x101a8 bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 isb ? type r/w reset depends on reset configuration sequence. bit16171819202122232425262728293031 partnum masknum type r reset ? table 2 . immr bit descriptions bits description settings isb 0?14 internal space base defines the base address of the internal memory space. the value of isb is configured at reset to one of seven addresses; the software can then change it to any value. the default address is based on the isb bits in the hard reset configuration word. the default is zero, which maps to address 0xf0000000. isb defines the 15 msbs of the memory map register base address. immr itself is mapped into the internal memory space region. as soon as the isb is written with a new base address, the immr base address is relocated according to the isb. isb enables the configuration of multiple-msc8101 systems. implementation-dependent ? 15 reserved. write to zero for future compatibility. partnum 16?23 part number this field is mask-programmed with a code corresponding to the part number of the part on which the siu is located. it helps factory test and user code that is sensitive to part changes. this field changes when the part number changes. for example, it would change if any new module is added or if the size of any memory module changes. it does not change if the part is changed to fix a bug in an existing module. the msc8101 has an id of 0x50. masknum 24?31 mask number this field is mask-programmed with a code corresponding to the mask number of the part on which the siu is located. it helps factory test and user code that is sensitive to part changes. it is programmed in a commonly changed layer and should be changed for all mask set changes. the msc8101 mask set 2k42a has an id of 0x02.
siu functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 5 3.1.2 2k87m mask set immr values immr identifies a specific device as well as the base address for the internal memory map. software can deduce availability and location of any on-chip system resources from the values in immr. partnum and masknum are mask programmed and cannot be changed for any particular device. 3.2 internal memory map mirror register (immmr) the 2k87m mask set adds a new internal memory map mirror register (immmr) which has a fixed address controlled by the qbus bank 1 (0x00f8ffc0) and the same register fields as the immr. it reflects the contents of the immr. if the isb in the immr is modified, the base address of all siu and cpm registers, including the immr, changes to the new value selected by the isb. in such a case, the device or external masters may not be able to access the registers. since the immmr does not reside in the same base memory area, it is always available at its fixed address. you can read the current isb value from the immmr and determine the current internal base address from that value. immr internal memory map register 0x101a8 bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 isb ? type r/w reset depends on reset configuration sequence. bit16171819202122232425262728293031 partnum masknum type r reset ? table 3 . immr bit descriptions bits description settings isb 0?14 internal space base defines the base address of the internal memory space. the value of isb is configured at reset to one of seven addresses; the software can then change it to any value. the default address is based on the isb bits in the hard reset configuration word. the default is zero, which maps to address 0xf0000000. isb defines the 15 msbs of the memory map register base address. immr itself is mapped into the internal memory space region. as soon as the isb is written with a new base address, the immr base address is relocated according to the isb. isb enables the configuration of multiple-msc8103 systems. implementation-dependent ? 15 reserved. write to zero for future compatibility. partnum 16?23 part number this field is mask-programmed with a code corresponding to the part number of the part on which the siu is located. it helps factory test and user code that is sensitive to part changes. this field changes when the part number changes. for example, it would change if any new module is added or if the size of any memory module changes. it does not change if the part is changed to fix a bug in an existing module. the msc8103 has an id of 0x50. masknum 24?31 mask number this field is mask-programmed with a code corresponding to the mask number of the part on which the siu is located. it helps factory test and user code that is sensitive to part changes. it is programmed in a commonly changed layer and should be changed for all mask set changes. the msc8103 mask set 2k87m has an id of 0x12.
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 6 freescale semiconductor reset 4 reset the 2k42a mask set offers two options for programming the hard reset configuration word (hrcw). the 2k87m mask set offers three options. in addition, the structure of the hrcw itself is different between the two mask sets. 4.1 reset configuration options ta bl e 4 shows the options for programming the hrcw for each of the mask sets. 4.1.1 configuration modes the 2k42a mask set defines the configuration modes as shown in ta bl e 5 . the 2k87m mask set adds a third ?reduced reset configuration? method of programming the reset configuration word, in addition to the host reset and hardware reset configuration methods. 4.1.2 reduced reset configuration information for mask set 2k87m reduced reset configuration is executed for serial boot only. only the nmi_out (bit 12), isb (bits 13?15), swdis (bit 26), and dlldis (bit 27) fields in the hard reset configuration word (hrcw) can be programmed using this method. the rest of the bits are programmed to their default values, but they can be reprogrammed later after reset. table 7 describes the 2k87m mask set hard reset configuration word. . table 4. hrcw programming options by mask set 2k42a 2k87m host reset . through the hdi16 from a host hardware reset . through the system bus from external memory host reset . through the hdi16 from a host. hardware reset . through the system bus from external memory. reduced reset . from a serial eprom using the i 2 c protocol. limited fields of the hard reset configuration word are configured via the appropriate data bus bits on the system bus. table 5. msc8101 2k42a mask set reset configuration modes rstconf hpe/ee1 btm[0-1]/ ee[4-5] mode 1 1 01 host reset configuration 0 0 00 master hardware reset configuration 1 0 00 slave hardware reset configuration table 6 . msc8103 2k87m mask set reset configuration modes rstconf hpe/ee1 btm[0-1]/ ee[4-5] mode 1 1 01 host reset configuration 0 0 00 master hardware reset configuration 1 0 00 slave hardware reset configuration 0 0 10 master reduced reset configuration 1 0 10 slave reduced reset configuration
reset functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 7 the major features of the reduce reset configuration include: the msc8103 samples the signals described in ta b le 6 at the rising edge of poreset . if the configured boot mode is serial, the values for the nmi_out, isb, swdis, and dlldis fields are programmed from the system data bus. the mapping of the bits on the data bus is the same as for hardware reset configuration mode. modck_h cannot be programmed using this method and the value is set by default to 000. therefore, only clock modes 0?1 and 4?7 can be used with this boot mode. in reduced configuration mode, the internal reset is extended for 1024 clkin cycles. although there is no default hrcw in this mode, the bits in the hrcw that are not programmed assume the default values. during the first 8 clkin cycles d[12?15] and d[26?27] are sampled to configure the nmi_out, isb, swdis, and dlldis fields in the hrcw. all other data bus bits are ignored. the simplest configuration scenario, where all data bus pins are ignored is not available for this mode. hreset in simple slave mode does not change the reset configuration. in master/slave mode, hreset does cause a new reset configuration. configuration from eprom for single or multiple chip is available only for the mentioned above 6 bits. all other bits on data bus are ignored. multiple chip configuration in a system with no eprom is also available only for the mentioned above 6 bits. all other bits on data bus are ignored. 4.2 hard reset configuration word changes the 2k87m mask set of the msc8103 adds the swdis field (bit 26) and changes the definition of the isb field (bits 13?15). msc8103 2k87m mask set hard reset configuration word bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 earb exmc irq7 int ebm bps scdis isps irpc dppc nmi out isb type r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit16171819202122232425262728293031 ? bbd mmr ? tcpc bc1pc swdis dlldis modck_h ? type r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 7. msc8103 2k87m mask set hard reset configuration word bit descriptions name reset description settings earb 0 0 external arbitration defines the initial value for ppc_acr[earb]. 0 = no external arbitration is assumed 1 = external arbitration is assumed exmc 1 0 external memc defines the initial value of br0[ememc]. 0 = no external memory controller is assumed 1 = external memory controller is assumed irq7 int 2 0 irq7 or int_out selection 0 = irq7 /int_out pin is irq7 1 = irq7 /int_out pin is int_out ebm 3 0 external 60x-compatible bus mode defines the initial value of bcr[ebm]. bps 4?5 0 boot port size defines the initial value of br0[ps], the port size for memory controller bank 0. 00 = 64-bit port size 01 = 8-bit port size 10 = 16-bit port size 11 = 32-bit port size
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 8 freescale semiconductor reset scdis 6 0 sc140 disabled enables/disables the sc140. this bit cannot be changed after reset. 0 = sc140 enabled 1 = sc140 disabled isps 7 0 internal space port size defines the initial value of bcr[isps]. this bit must be set in order to use the host interface. setting isps configures the msc8103 to respond to accesses from a 32-bit external master to its internal space. this bit cannot be changed after reset. 0 = 60x-compatible data bus is 64 bits wide 1 = 60x-compatible data bus is 32 bits wide (lower 32 bits; upper 32 bits reserved for hdi16 irpc 8?9 0 interrupt pin configuration defines the initial value of siumcr[irpc]. dppc 10?11 0 data parity pin configuration defines the initial value of siumcr[dppc]. nmi out 12 0 nmi out defines the host core to handle a non-maskable interrupt (nmi) event. 0 = nmi is serviced by sc140 core 1 = nmi is routed to external pin and serviced by the external host isb 13?15 0 initial internal space base select defines the initial value of immr(isb[0?14]) and determines the base address of the internal memory space and the dspram base address on the local bus. note that the sc140 core internal address space spans from 0x00000000 ? 0x00ffffff (16 mb). therefore it is not advisable to map the internal memory map register (immr) in this space, since the sc140 core cannot access the registers of the siu and cpm. qbus banks are mapped to address 0x00f00000, so using isb value 101 causes the dual-port ram (dpram) address space and the qbus address space to overlap. modifying the qbus base registers to another address allows the user to access the dpram address space. isb internal memory dspram (bank 10) 000 0xf0000000 0x02000000 001 0xf0f00000 0x03000000 010 0xff000000 0x04000000 011 0xfff00000 0x05000000 100 reserved reserved 101 0x00f00000 0x07000000 110 0x0f000000 0x08000000 111 0x0ff00000 0x09000000 note: the 2k87m mask adds the dspram location to the areas controlled by these bits. ? 16 0 reserved. write to zero for future compatibility. bbd 17 0 bus busy disable defines the initial value of siumcr[bbd]. mmr 18?19 0 mask masters requests defines the initial value of siumcr[mmr]. ? 20?21 0 reserved. write to zero for future compatibility. tcpc 22?23 0 transfer code pin configuration defines the initial value of siumcr[tcpc]. bc1pc 24?25 0 bc1pc value defines the initial value of siumcr[bc1pc]. swdis 26 0 software watchdog disable defines the initial state of the software watchdog timer 0 = software watchdog timer enabled 1 = software watchdog timer disabled note: this field is undefined in the 2k42a mask set. dlldis 27 0 dll disable defines whether the dll mechanism is disabled. 0 = no dll bypass 1 = dll bypass modck_h 28?30 0 modck high order bits high-order bits of the modck bus, which determine the clock reset configuration. ? 31 0 reserved. write to zero for future compatibility. table 7. msc8103 2k87m mask set hard reset configuration word bit descriptions (continued) name reset description settings
boot functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 9 5boot the 2k42a mask set does not support a serial boot mode. the 2k87m mask set supports a serial boot mode with a reduced reset configuration. the following sections describe the serial boot mode operations. 5.1 boot mode definition changes the boot modes for mask set 2k42a are defined by the values of btm[0?1] when sampled on the rising edge of poreset , as follows: the boot modes for mask set 2k87m are defined by the values of btm[0?1] when sampled on the rising edge of poreset , as follows: 5.2 serial eprom boot procedure the msc8103 core programs the i 2 c registers and parameter ram and prepares buffers and buffer descriptors (bds) for the boot loading process. the msc8103 i 2 c interface is programmed as the master, and it accesses the slave address 0b1010111 to read the boot source code. booting the msc8103 through the serial eprom is useful for systems in which the msc8103s are connected only through serial interfaces, such as tdm, ethernet, atm, and so forth. note: the bootloader supports access to serial eproms with a user-defined device address and 2-byte address specifications. 5.3 software watchdog handling the software watchdog timer can be enabled by clearing the swdis bit as part of the reduced reset configuration process. in serial boot mode, if the swdis bit is cleared, the bootloader program periodically executes a special service sequence to prevent the time-out of its counter and the assertion of a hardware reset during the bootloading process. for details on the software watchdog, refer to section 4.2.5 , software watchdog timer , and section 4.3 , siu programming model in the msc8103 reference manual . btm0 btm1 boot source 0 0 external memory 0 1 hdi16 10 reserved 11 reserved btm0 btm1 boot source 0 0 external memory 0 1 hdi16 1 0 serial interface 11 reserved
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 10 freescale semiconductor boot 5.4 source program data stream structure the source program can be organized into several blocks. each block can be either a data block or an instruction block, and it can be loaded to a different specified destination. each block contains the block size, the location where the block is loaded, source program words, checksum, checksum enable and the location from which the next block is loaded. when each block word is loaded, the routine calculates a checksum by xoring the current word bit by bit with the result of xoring previous words. the value of bit i of the current result is equal to xoring bit i of the current word with bit i of the previous result. after the entire block is loaded, the calculated checksum is compared to the loaded checksum. the checksum comparison and calculation can be skipped by clearing checksum enable bit. the last block is a special block that indicates end of code. it contains the boot execution start address. figure 1 shows the stream structure. 5.5 source program block structure the data stream source programs must be structured in the format shown in table 8 . figure 1. boot code stream structure table 8. block structure word description 1 block size + checksum enable bit (see figure 2 for layout description) 2 next block address 3 address where the first block of the source program is to be loaded, most significant part 4 address where the first block of the source program is to be loaded, least significant part 5 first word of source program n last word of source program n + 1 checksum?xor for first block n + 2 checksum?xor for first block 2nd offset + 1 block size + checksum enable bit 2nd offset + 2 next block address 2nd offset + 3 address where the second block of the source program is to be loaded, most significant part 2nd offset + 4 address where the second block of the source program is to be loaded, least significant part 2nd offset + 5 first word of source program 2nd offset + n last word of source program 2nd offset +n + 1 checksum?xor for second block 2nd offset + n + 2 checksum ?xor for second block block 1 block 2 . . . block x code end block
boot functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 11 in addition, the following rules apply: the source data must be in big-endian format, with the most significant part at the lower-order address. to enable checksum, set the cse bit. to disable checksum, clear the cse bit. block size includes the checksum and checksum . each address must be aligned on a 16-byte boundary. maximum size for a block is 64 kb. checksum is performed on all block words, including addresses and sizes. the block size should be a multiple of 32 bits. if the next block address is 0x0, the bootloader treats the next block as sequential. all addresses should be located in sram. the address should be given as a dsp internal address. the end of the boot code stream is indicated by a special boot end block with the structure shown in ta bl e 9 . the first two words indicate the end of the source blocks. at least one block of source code must be loaded when the bootloader is invoked. the boot start address indicates the address at which the boot program execution starts. this address must be aligned on a 16-byte boundary. the bootloader routine expects at least one code block in addition to the boot end block. the sequence is repeated for subsequent blocks, until the final block in the data stream is reached. 5.6 load procedure the bootloader program uses the i 2 c serial interface to access data in the eprom and to program the i 2 c parameter ram and registers. the i 2 c uses bds and buffers to read and write data. the bootloader prepares and keeps track of the bds and buffers for program loading. to enable multi-master support, the first 14 bytes of the eprom are reserved for an address table, which is also accessed in single-master mode. the table entries contain the location of the boot code.the loading process starts by calculating the entry address and reading the boot code location address. then the code loading starts by reading the first 4 block words from the eprom. the size of block, where to load it, the location of the next block in eprom, and checksum enable are extracted. bit 0 123456789101112131415 description cse 1 block size notes: 1. cse = checksum enable. set this bit when a checksum comparison is needed. 2. since the eproms that support the i 2 c protocol are small, 15 bits are sufficient to define the block size. figure 2. checksum enable bit + block size table 9. structure of the boot end block word description 10x0000 20x0000 3 boot start address, most significant part 4 boot start address, least significant part 50x0000 60x0000 7 checksum?xor 8 checksum ?xor
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 12 freescale semiconductor boot note: the bootloader supports access to serial eproms up to 512 kb with an address specification that is accessed by 2 bytes. the bootloader allocates a buffer for the first code block according to the address and size given in the opening 4 words and creates a bd that describes it. after the bd is ready, the bootloader starts reading the code block from the eprom. if checksum is enabled, the bootload calculates a checksum on the block word and compares the calculated checksum to the loaded checksum. if the checksum is correct, the bootloader continues to the next block. if the checksum fails, the bootloader tries to read the block again. after a second unsuccessful try, the bootloader aborts. to skip the checksum comparison, clear the checksum enable bit. if checksum is disabled, the bootloader program continues loading the next code block after finishing the current one. when all code blocks are loaded, boot execution starts from the start address given in the end block. the bootloader program polls the bds to check when a code block has been received. it does not use interrupts. the load procedure is described in figure 3 . figure 3. serial boot load procedure load from serial eprom configure i 2 c register and parameter ram disable software watchdog get 4 first words first 32 bytes = 0? ok? read block checksum enabled? enabled? no go to end loading yes no read block and calculate checksum checksum ok? enabled? first error? ok? yes error- stop boot no yes prepare next block address no go to end loading read end block start boot execution calculate table address
boot functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 13 5.7 i 2 c clocking the msc8103 i 2 c interface accesses the serial eprom using a clock frequency derived by dividing the core frequency by 4000. this division sets the i 2 c clock to 75 khz or less, a clock frequency that most eproms support. if the msc8103 i 2 c gets an nak during transmission, that is, the eprom does not respond to the address asserted by msc8103, the boot loader stops execution. if the software watchdog timer is enabled, the counter will eventually expire causing a system reset. after reset, the bootloading process restarts. 5.8 reset configuration word the only reset configuration mode that can be used while serial boot mode is enabled is reduced configuration word. in the reduced configuration word, only the nmi_out, isb, swdis, and dlldis fields can be set. for details, see section 4.1.2 . 5.9 default programming during boot the bootloader routine provides default programming for parts of the msc8103. the routine programs the upmc and the gpcm as required to support the internal sram and peripherals. the upmc is programmed to support the bus-to-cpm clock ratio. the routine checks the value of the scmr[busdf] bits and selects the bus-to-cpm clock ratio. the routine also programs the correct values for the elir[a?f] registers in the programmable interrupt controller (pic) to determine the interrupt mode (edge-triggered or level-triggered). 5.10 multi-processor booting from a serial eprom the i 2 c protocol supports multi-master environments. all msc8103 booting devices act as i 2 c masters and try to access the serial eprom. the first 14 bytes of the serial eprom are reserved for an address table. each master accesses a different entry in the table according to its isb[0?2] bits in the immr, allowing seven i 2 c masters in the system. each entry in the table contains the actual address where the boot program resides in the 2-byte increments. the master accesses the table, reads the boot location address, and starts loading boot from there.if two or more masters try to put information onto the bus, the first to produce a 1 when another produces a 0 loses the arbitration (collision). if a collision occurs, the master that loses the arbitration retries. note: if there are less than seven masters and not all 14 bytes of the table are needed, the boot code can start inside the first 14 bytes of the table. a msc8103 i 2 c master should access a table entry equal to its isb[0?2] value multiplied by two. the bootloading process always starts by accessing the address table. in a single master environment, the boot code may start immediately after the address entry. note: during the booting process, multiple masters should not address each other. there is no support for multi- master errors. 5.11 boot code changes the boot code for the 2k87m mask set supports the i 2 c protocol. in addition, the code reflects changes in the device design that fix a host checksum errata, make the sram base address isb dependent, and allow the software watchdog timer to be enabled or disabled via software. for a detailed listing of the updated boot code, see appendix a .
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 14 freescale semiconductor clock system 6 clock system 6.1 clock scheme modifications the msc8101 mask set 2k42a and the msc8103 mask set 2k87m use different clock schemes. the following paragraphs describe the clock schemes. 6.1.1 mask set 2k42a clock scheme six bit values map the msc8101 clocks to one of the valid configuration mode options. each option determines the clkin , sc140 core, system bus, scc clock, cpm, and clkout frequencies. the six bit values are derived from three dedicated input pins ( modck[1?3] ) and three bits from the reset configuration word (modck_h). to configure the spll pre-division factor, spll multiplication factor, and the frequencies for the sc140 core, scc clocks, cpm parallel i/o ports, and system buses, the modck[1?3] pins are sampled and combined with the modck_h values when the internal power-on reset (internal poreset ) is deasserted. clock configuration changes only when the internal poreset signal is deasserted. the following factors are configured: spll pre-division factor (spll pdf) spll multiplication factor (spll mf) bus post-division factor (bus df) figure 4 shows the functional block diagram for the 2k42a mask set. the 2k42a mask set contains an internal system phase-lock loop (spll) the scc division factor (scc df) is fixed at 4 and the cpm division factor (cpm df) is fixed at 2. the brg division factor (brg df) is configured through the system clock control register (sccr) and can be 4, 16 (default after reset), 64, or 256. figure 4. msc8101 clock functional block diagram for 2k42a mask set system bus clock cpm clock clkin 2 f cpm 2 f cpm scc clock brg clock clkout sc140 core clock bus df scc df spll pdf spll mf brg df cko df cpm df dll internal clocks note: spll pdf determined by the clock configuration mode; spll mf determined by the clock configuration mode; bus df = clkout df and is 4 or 5, determined by the clock configuration mode; scc df is always 4; cpm df is always 2; brg df is set by the system clock control register (sccr) and is 4, 16 (default), 64, or 256. key: spll pdf: system pll pre-division factor spll mf: system pll multiplication factor dll: delay lock loop bus df: bus division factor scc df: scc division factor cpm df: cpm division factor brg df: baud rate generator division factor cko df: clkout division factor dllin
clock system functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 15 6.1.2 mask set 2k87m clock scheme six bit values map the msc8101 clocks to one of the valid configuration mode options. each option determines the clkin , sc140 core, system bus, scc clock, cpm, and clkout frequencies. the six bit values are derived from three dedicated input pins ( modck[1?3] ) and three bits from the hard reset configuration word (modck_h). to configure the spll pre-division factor, spll multiplication factor, and the frequencies for the sc140 core, scc clocks, cpm parallel i/o ports, and system buses, the modck[1?3] pins are sampled and combined with the modck_h values when the internal power-on reset (internal poreset ) is deasserted. clock configuration changes only when the internal poreset signal is deasserted. the following factors are configured: spll pre-division factor (spll pdf) spll multiplication factor (spll mf) bus post-division factor (bus df) cpm division factor (cpm df) core division factor (core df) cpll pre-division factor (cpll pdf) cpll multiplication factor (cpll mf) figure 5 shows the functional block diagram for the 2k87m mask set. the 2k87m mask set contains an internal system phase-lock loop (spll) and a core phase-lock loop (cpll). figure 5. msc8103 clock functional block diagram for 2k87m mask set system bus clock cpm clock clkin scc clock brg clock clkout sc140 bus df scc df spll pdf spll mf brg df cko df cpm df dll internal clocks note: spll pdf, spll mf, core df, cpll pdf, cpllmf, and cpm df are determined by the clock configuration mode; bus df = cko df and is determined by the clock configuration mode; scc df is always 4; brg df is set by the system clock control register (sccr) and is 4, 16 (default), 64, or 256. key: spll pdf: system pll pre-division factor spll mf: system pll multiplication factor dll: delay lock loop bus df: bus division factor scc df: scc division factor cpm df: cpm division factor brg df: baud rate generator division factor cko df: clkout division factor core df: core division factor cpll pdf: core pll pre-division factor cpll mf: core pll multiplication factor dllin core df cpll pdf cpll mf core clock core pll system pll
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 16 freescale semiconductor clock system 6.2 system clock mode register (scmr) changes the 2k42a and 2k87m mask sets use different scmr definitions. the following sections describe the scmr definitions for each mask set. 6.2.1 2k42a mask set scmr field definitions scmr is a read-only register that is updated during power-on reset (poreset) and provides the mode control signals to the plls, dll, and clock logic. this register reflects the currently defined configuration settings. bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ? corepdf coremf busdf cpmdf type r reset ? bit16171819202122232425262728293031 spllpdf spllmf ? dlldis ? type r reset ? figure 6. 2k42a mask set system clock mode register (scmr)? 0x10c88 table 10. 2k42a mask set scmr bit descriptions name bit no. defaults description settings poreset hard reset ? 0?1 ??reserved corepdf 2?3 configuration pins unaffected core pll pre-division factor not used. coremf 4?7 configuration pins unaffected core multiplication factor not used busdf 8?11 configuration pins unaffected 60x bus division factor 0010 bus df = 3 0011 bus df = 4 0100 bus df = 5 all other combinations not used. cpmdf 12?15 configuration pins unaffected cpm division factor 0001 cpm df = 2 all other combinations are not used. spllpdf 16?19 configuration pins unaffected spll pre-division factor 0000 spll pdf = 1 0001 spll pdf = 2 0010 spll pdf = 3 0011 spll pdf = 4 all other combinations not used spllmf 20?23 configuration pins unaffected spll multiplication factor 0110 spll mf = 12 0111 spll mf = 14 1000 spll mf = 16 1001 spll mf = 18 1010 spll mf = 20 1011 spll mf = 22 1100 spll mf = 24 1101 spll mf = 26 1110 spll mf = 28 1111 spll mf = 30 all other combinations not used ? 24 ??reserved dlldis 25 configuration pins unaffected dll disable 0 dll operation is enabled 1 dll is disabled
clock system functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 17 6.2.2 2k87m mask set scmr field definitions scmr is a read-only register that is updated during power-on reset (poreset) and provides the mode control signals to the plls, dll, and clock logic. this register reflects the currently defined configuration settings. ? 26?31 ??reserved bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 corepdf coremf busdf cpmdf type r reset ? bit16171819202122232425262728293031 spllpdf spllmf ? dlldis ? coredf type r reset ? figure 7. 2k87m mask set system clock mode register (scmr)? 0x10c88 table 11. 2k87m mask set scmr field descriptions name bit no. defaults description settings poreset hard reset corepdf 0?3 configuration pins unaffected core pll pre-division factor 0000 cpll pdf = 1 0001 cpll pdf = 2 0010 cpll pdf = 3 0011 cpll pdf = 4 all other combinations not used. coremf 4?7 configuration pins unaffected core multiplication factor 0101 cpll mf = 10 0110 cpll mf = 12 0111 cpll mf = 14 all other combinations not used. busdf 8?11 configuration pins unaffected 60x-compatible bus division factor 0001 bus df = 2 0010 bus df = 3 0011 bus df = 4 0100 bus df = 5 0101 bus df = 6 all other combinations not used. cpmdf 12?15 configuration pins unaffected cpm division factor 0000 cpm df = 1 0001 cpm df = 2 0010 cpm df = 3 all other combinations not used. spllpdf 16?19 configuration pins unaffected spll pre-division factor 0000 spll pdf = 1 0001 spll pdf = 2 0010 spll pdf = 3 0011 spll pdf = 4 0100 spll pdf = 5 0101 spll pdf = 6 all other combinations not used table 10. 2k42a mask set scmr bit descriptions (continued) name bit no. defaults description settings poreset hard reset
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 18 freescale semiconductor clock system 6.3 system clock control register (sccr) the 2k87m mask set adds a new field (clkodis) to the sccr. the functionality of the common field (dfbrg) is the same. figure 8 shows the register layout and table 12 lists the bit descriptions. spllmf 20?23 configuration pins unaffected spll multiplication factor 0101 spll mf = 10 0110 spll mf = 12 0111 spll mf = 14 1000 spll mf = 16 1001 spll mf = 18 1010 spll mf = 20 1011 spll mf = 22 1100 spll mf = 24 1101 spll mf = 26 1110 spll mf = 28 1111 spll mf = 30 all other combinations not used ? 24 ??reserved dlldis 25 configuration pins unaffected dll disable 0 dll operation is enabled 1 dll is disabled ? 26?27 ??reserved coredf 28?31 configuration pins unaffected core division factor 0000 core df = 1 0001 core df = 2 0010 core df = 3 0011 core df = 4 0100 core df = 5 0101 core df = 6 all other combinations not used. bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ? type reserved reset ? bit16171819202122232425262728293031 ? clkodis ?dfbrg type reserved r/w reserved r/w reset ? 0 ? 0 1 figure 8. system clock control register (sccr)? 0x10c80 table 12. sccr bit descriptions name bit no. defaults description settings poreset hard reset ? 0?26 ? ? reserved. write to 0 fro future compatibility. clkodis 27 0unaffected clkout disable disables the clkout signal. the value of clkout when disabled is indeterminate (can be 1 or 0). 0 clkout enabled (default) 1 clkout disabled note : this bit is reserved in mask set 2k42a. table 11. 2k87m mask set scmr field descriptions (continued) name bit no. defaults description settings poreset hard reset
clock system functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 19 6.4 clock mode changes 6.4.1 2k42a mask set clock configuration modes the msc8101 2k42a mask set supports the following valid clock modes: 6.4.2 2k87m mask set clock modes the msc8103 2k87m mask set supports the clock modes listed in ta bl e 1 4 . ? 28?29 ? ? reserved. write to 0 fro future compatibility. dfbrg 30?31 01 unaffected division factor for the brg clock defines the brgclk frequency. changing this value does not result in a loss of lock condition. 00 divide by 4 01 divide by 16 (default value) 10 divide by 64 11 divide by 256 table 13. 2k42a mask set clock configuration modes mode # modck_h modck[1?3] spll pdf spll mf bus df ratio bus:cpm:core bus/ clkin 46 101 110 2 16 4 1 : 2 : 4 4 57 111 001 2 10 5 1 : 2.5 : 5 1 table 14. 2k87m mask set clock configuration modes mode # modck_h 1 modck[1?3] 2 spll pdf spll mf bus df core df cpm df cpll pdf cpll mf ratio bus:cpm:core bus/ clkin 0 000 000 1 12 4 4 2 4 12 1 : 2 : 3 3 1 000 001 2 16 4 4 2 4 12 1 : 2 : 3 2 2 000 010 reserved 3 000 011 reserved 4 000 100 2 16 4 4 2 4 14 1 : 2 : 3.5 2 5 000 101 1 12 4 2 2 5 10 1 : 2 : 4 3 6 000 110 3 12 4 2 2 5 10 1 : 2 : 4 1 7 000 111 1 10 5 5 2 2 10 1 : 2.5 : 5 2 8 001 000 1 16 4 4 2 4 12 1 : 2 : 3 4 9 001 001 1 20 4 4 2 4 12 1 : 2 : 3 5 10 001 010 3 12 4 4 2 4 12 1 : 2 : 3 1 11 001 011 3 12 4 4 2 4 14 1 : 2 : 3.5 1 12 001 100 1 12 4 4 2 4 14 1 : 2 : 3.5 3 13 001 101 1 16 4 4 2 4 14 1 : 2 : 3.5 4 14 001 110 reserved 15 001 111 reserved 16 010 000 1 12 6 2 2 5 10 1 : 3 : 6 2 17 010 001 2 12 6 2 2 5 10 1 : 3 : 6 1 18 010 010 1 16 8 8 2 2 12 1 : 4 : 6 2 19 010 011 2 16 8 8 2 2 12 1 : 4 : 6 1 20 010 100 reserved 21 010 101 reserved table 12. sccr bit descriptions (continued) name bit no. defaults description settings poreset hard reset
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 20 freescale semiconductor clock system 22 010 110 reserved 23 010 111 reserved 24 011 000 2 12 6 6 2 3 12 1 : 3 : 4 1 25 011 001 1 12 6 3 2 5 10 1 : 3 : 4 2 26 011 010 1 18 6 3 2 5 10 1 : 3 : 4 3 27 011 011 2 10 5 3 2 5 12 1 : 2.5 : 4 1 28 011 100 reserved 29 011 101 reserved 30 011 110 reserved 31 011 111 2 12 6 8 2 3 12 1 : 3 : 3 1 32 100 000 reserved 33 100 001 2 16 8 8 4 2 10 1 : 2 : 5 1 34 100 010 1 12 4 4 2 2 10 1 : 2 : 5 3 35 100 011 2 16 8 8 4 2 12 1 : 2 : 6 1 36 100 100 1 16 8 8 4 2 12 1 : 2 : 6 2 37 100 101 reserved 38 100 110 reserved 39 100 111 reserved 40 101 000 reserved 41 101 001 reserved 42 101 010 reserved 43 101 011 reserved 44 101 100 reserved 45 101 101 reserved 46 3 101 110 2164 2 2 510 1 : 2 : 4 2 47 101 111 reserved 48 110 000 reserved 49 110 001 reserved 50 110 010 reserved 51 110 011 reserved 52 110 100 reserved 53 110 101 reserved 54 110 110 reserved 55 110 111 reserved 56 111 000 reserved 57 3 111 001 2 10 5 5 2 2 10 1 : 2.5 : 5 1 58 111 010 reserved 59 111 011 reserved 60 111 100 reserved 61 111 101 reserved 62 111 110 reserved 63 111 111 reserved notes: 1. modck_h is a 3-bit field that occupies bits 28?30 of the hard reset configuration word. the bits are listed in the table in the following order: bit 28, bit 29, bit 30. for example, the value 110 indicates that bit 28 = 1, bit 29 = 1, and bit 30 = 0. 2. modck[1?3] are external signal inputs that are either pulled up (1) or pulled down (0) to configure the system clock mode. the values are listed in the table in the following order: modck1, modck2, modck3. for example, the value 110 indicates that modck1 is pulled up, modck2 is pulled up, and modck3 is pulled down. 3. this mode is compatible with the same mode for mask set 2k42a. table 14. 2k87m mask set clock configuration modes (continued) mode # modck_h 1 modck[1?3] 2 spll pdf spll mf bus df core df cpm df cpll pdf cpll mf ratio bus:cpm:core bus/ clkin
clock system functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 21 6.5 clkin-to-clkout delay change for the 2k42a mask set, the clkin -to- clkout delay is a function of frequency. for the 2k87m mask set, the clkin -to- clkout delay is a not a function of frequency. therefore, the two versions cannot be used together in a dll-disabled system. 6.6 enabling the dll for the 2k42a, system erratum qsiu14 requires that the msc8101 use only dll-disabled mode and a zero-delay buffer. to use the msc8103 mask set 2k87m in such a design with the dll-enabled, the zero-delay buffer must either be placed in pll-bypass mode or replaced. 6.7 disabling the dll the 2k87m ac timing specification listed in the msc8103 technical data sheet is for dll-enabled mode only and is therefore referenced to dllin . for 2k87m clock modes 5, 6, 46, and 57 only, apply the following offsets to accommodate for the fact that the signal is referenced to clkout instead of dllin : for siu outputs, add 400 ps. for dma outputs, add 400 ps to specification 76. for siu inputs, subtract 400 ps. for dma inputs, subtract 400 ps from specifications 72?75. 6.8 clock frequency changes lists the maximum clock frequencies for each mask set. note: refer to msc8103 technical data for details on all frequency ranges and limitations. table 1 5. maximum clock frequencies for each mask set clock 2k42a maximum frequency 2k87m maximum frequency input clock (clkin) 68.75 mhz 75 mhz internal bus clock (bclk) 68.75 mhz 100 mhz output clock (clkout) 68.75 mhz 100 mhz scc clock (sclk) 68.75 mhz 100 mhz cpm clock (cpmclk) 137.5 mhz 200 mhz sc140 core clock (dspclk) 275 mhz 300 mhz
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 22 freescale semiconductor memory map 7 memory map the 2k87m mask adds the immmr to the memory map. the 2k87m memory map for bank1 of the qbus is shown in ta bl e 1 6 . 8 orx in upm mode in upm mode, the 2k42a mask uses the previously undefined bit 27 in the orx to add a wait state to the memory cycle when set. in the 2k87m mask set, this bit is undefined. 9hdi16 the 2k87m mask set defines additional bits in the interface control register (icr) and interface status register (isr) to support hdi16 bursts of various sizes. this affects the conditions used to assert or deassert the hreq signal. the following sections compare the register layouts for the two mask sets and indicate the changes to the logic used to assert the hreq signal. 9.1 interface control register (icr) changes the following sections list the icr layout and definitions for the 2k42a and 2k87m mask sets. 9.1.1 2k42a mask set icr definitions table 16. mask set 2k87m qbus memory map?bank1 sc140 core internal address mnemonic name size boot rom 0000?07ff bootrom msc8103 boot rom 2 kb 0800?ffbf reserved leave unchanged for future compatibility 63 kb ? 64 bytes ffc0 immmr internal memory map mirror register 32 bits ffc4?ffff reserved leave unchanged for future compatibility 60 bytes icr mask set 2k42a interface control register (dma = 0, hicr = 1) 0x0 bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ? hf0 hf1 ? init hm hf2 hf3 hdrq treq rreq type r/w reset see table 18 on page 25 icr mask set 2k42a interface control register (dma = 1, hicr = 1) 0x0 bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ? hf0 hf1 ? init hm hf2 hf3 ? treq rreq type r/w reset see table 18 on page 25
hdi16 functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 23 icr is a read/write control register that allows the use of bit manipulation instructions on control register bits. the host processor uses the icr to control the hdi16 interrupts and flags. the sc140 core cannot access the icr. the hpcr[dma] bit and the hcr[hicr] bit control the function of the icr bits. icr mask set 2k42a interface control register (dma = 0, hicr = 0) 0x0 bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ? hf0 hf1 ? init hdm hf2 hf3 hdrq treq rreq type r/w r r/w reset see table 18 on page 25 icr mask set 2k42a interface control register (dma = 1, hicr = 0) 0x0 bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ? hf0 hf1 ? init hdm hf2 hf3 ? note 1 note 2 type r/w r r/w r/w reset see table 18 on page 25 notes: 1. hdm0 when read, treq when written 2. hdm0 when read, rreq when written table 17. mask set 2k42a icr bit descriptions name description ? 0?4 reserved. write to zero for future compatibility. hf0 5 host flag 0 a general-purpose flag for host-to-core communication. the host processor can set or clear hf0. hf0 is reflected in the hsr on the core side of the hdi16. hf1 6 host flag 1 a general-purpose flag for host-to-core communication. the host processor can set or clear hf1. hf1 is reflected in the hsr on the core side of the hdi16. ? 7 reserved. write to zero for future compatibility. init 8 force initialization used by the host processor to force initialization of the hdi16 hardware (which may or may not be necessary, depending on the software design of the interface). during initialization, the hdi16 transmit and receive control bits are configured. the t ype of initialization performed when the init bit is set depends on the state of treq and rreq in the hdi16. the init command, which is local to the hdi16, conveniently configures the hdi16 into the desired data transfer mode. the effect of the init command is described in ta ble 19 . when the host sets the init bit, the hdi16 hardware executes the init command. the interface hardware clears the init bit after the command executes.
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 24 freescale semiconductor hdi16 hm/hdm 9?10 host mode/host dma mode when host dma mode is enabled, if hcr[hicr] is set, the hreq pin requests dma transfers, the treq and rreq bits select the direction of dma transfers, and the hack input pin is used as a dma transfer acknowledge input, if oae in hpcr is cleared. if the dma direction is from core to host, the contents of the selected register are written to the host data bus w hen hack is asserted. if the dma direction is from host to core, the selected register is read from the host data bus when hack is asserted. if hpcr[oae] is set, a host read or write to host address 0x4 is used as a dma transfer acknowledge. if the dma direction is from core to host, the contents of the selected register are written to the host data bus when the host reads from host address 0x4. if the dma direction is from host to core, the selected register is read from the host data bus when the host writes to ho st address 0x4. hm also controls the size of the dma word to be transferred. the hdi16 data register selected during a host dma transfer is determined by a 2-bit address counter, which is preloaded with the value in hm. the address counter replaces the ha[0?1] bits of the hdi16 during a host dma transfer. the address counter can be initialized with the init bit feature. after each dma transfer on the host data bus, the address counter is decremented. when the address counter reaches the last register, the address counter is loaded with the value in hm. thus, 16-bit, 32-bit, 48-bit, or 64-bit data can be transferred in a circular fashion, and the need is eliminated for the dma controller to supply the ha0?2] pins (hpcr bit oae=0) or to read/write at host address 0x4 (hpcr bit oae=1). for 32-, 48- or 64-bit data transfers, the core cpu interrupt rate is reduced by a factor of 2, 3, or 4, respectively, from the host request rate. that is, for every two or three host processor data transfers of one byte each, there is only one 64-bit core cpu interru pt. this bit is available only in icr mode (hcr[hicr] = 1). when the hdi16 is in icr priority non-dma mode (the hpcr[dma] bit is cleared and hcr[hicr] is set), data transfer size is defined by hm, as described in ta ble 22 . the transfer size causes the rx x /tx x register read/write at the last (trigger) address to clear the rxdf/txde bits, respectively. hf2 11 host flag 2 a general-purpose flag for host-to-core communication. the host processor can set or clear hf2. hf2 is reflected in the hsr on the core side of the hdi16. hf3 12 host flag 3 a general-purpose flag for host-to-core communication. the host processor can set or clear hf3. hf3 is reflected in the hsr on the core side of the hdi16. hdrq 13 hreq/htrq and hack/hrrq pin control controls the hreq/htrq and hack/hrrq pins. if hdrq is cleared, the hreq/htrq pin functions as a single hreq. if hdrq is set, the hreq/htrq and hack/hrrq pins function as htrq and hrrq, respectively. this bit is available only in non-dma (interrupt) mode (hpcr[dma] = 0). treq/hdm0 14 hreq/htreq pin control controls the hreq/htreq pin for host transmit data transfers. in non-dma (interrupt) mode (dma = 0 in the hpcr), treq enables host requests via the host request (hreq or htrq) pin when the transmit data register empty (txde) status bit in the isr is set. if treq is cleared, txde interrupts are disabled. if treq and txde are set, the host request pin is asserted. in dma modes (hpcr[dma] = 1 and hcr[hicr] = 1), software must set or clear treq to select the direction of dma transfers. setting treq sets the direction of the dma transfers as host-to-core and enables the hreq pin to request data transfers. when hcr[hicr] is cleared and hpcr[dma] is set, a treq read reflects the status of not hdm0 in hcr. when written, treq affects the init mode. see table 20 . rreq/hdm0 15 hreq and hrreq pin control controls the hreq and hrreq pins for host receive data transfers. in non-dma (interrupt) mode (hpcr[dma] = 0), rreq enables host requests via the host request (hreq or hrrq) pin when the receive data register full (rxdf) status bit in the isr is set. if rreq is cleared, isr[rxdf] interrupts are disabled. if rreq is set, the host request pin (hreq or hrrq) is asserted if isr[rxdf] is set. in host dma mode (dma = 1 in the hpcr and hicr = 1 in the hcr), rreq must be set or cleared by software to select the direction of dma transfers. setting rreq sets the direction of the host dma transfers to core-to-host and enables the hreq pin to request data transfers. when hicr in hcr is cleared and dma in hpcr is set, rreq, when read, reflects the status of hdm0 in hcr. when hcr[hicr] is cleared and hpcr[dma] is cleared, an rreq read reflects the status of hcr[hdm0]. when written, rreq affects the init mode. see table 20 . table 17. mask set 2k42a icr bit descriptions (continued) name description
hdi16 functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 25 ta bl e 1 8 shows the result of the four kinds of reset on bits in each of the hdi16 registers accessible to the host processor. the hardware reset is caused by asserting the reset signal. the individual reset is caused by clearing hpcr[hen]. ta bl e 1 9 shows the effects of the init command in relation to the values of treq and rreq. ta bl e 2 0 and ta bl e 2 1 summarize the effect of rreq and treq on the hreq and hrrq signals. table 18. host-side registers after reset register name register data reset type hardware (hw) reset individual (ir) reset icr all bits 0 ? cvr nmi 0 0 hc 0 0 hv[0?6] 0 ? isr hreq 0 1 if treq is set; 0 otherwise hf[4?7] 0 ? trdy 1 1 txde 1 1 rxdf 0 0 rx rx[0?3] empty empty tx tx[0?3] empty empty table 19. effects of the init command treq rreq after init execution transfer direction initialized 0 0 init = 0 none 0 1 init = 0; isr[rxdf] = 0; hsr[htfe/htfnf] = 1 core to host 1 0 init = 0; isr[txde] = 1; hsr[hrff/hrfne] = 0 host to core 1 1 init = 0; isr[rxdf] = 0; hsr[htfe/htfnf] = 1; isr[txde] = 1; hsr[hrff/hrfne] = 0 host to/from core table 20. treq and rreq modes (hdrq = 0) in non-dma mode (hicr=1) treq rreq hreq signal 0 0 no interrupts (polling) 0 1 isr[rxdf] request (interrupt) 1 0 isr[txde] request (interrupt) 1 1 isr[rxdf] and isr[txde] request (interrupts) table 21. treq and rreq modes (hdrq = 1) in non-dma mode (hicr=1) treq rreq htrq signal hrrq signal 0 0 no interrupts (polling) no interrupts (polling) 0 1 no interrupts (polling) isr[rxdf] request (interrupt) 1 0 isr[txde] request (interrupt) no interrupts (polling) 1 1 isr[txde] request (interrupt) isr[rxdf] request (interrupt)
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 26 freescale semiconductor hdi16 ta bl e 2 2 shows the valid hm values and their meaning. 9.1.2 2k87m mask set icr definitions table 22. hm host dma mode values (hicr=1) hm mode 0 1 dma mode non-dma mode 0 0 16-bit words 64-bit words. last read/write (trigger) address: 0x4 0 1 32-bit words 48-bit words. last read/write (trigger) address: 0x5 1 0 48-bit words 32-bit words. last read/write (trigger) address: 0x6 1 1 64-bit words 16-bit words. last read/write (trigger) address: 0x7 icr 2k87m mask set interface control register (dma = 0, hicr = 1) 0x0 bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 hrra htra ? hf0 hf1 ? init hm hf2 hf3 hdrq treq rreq type r/w reset see table 24 on page 29 icr 2k87m mask set interface control register (dma = 1, hicr = 1) 0x0 bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 hrra htra ? hf0 hf1 ? init hm hf2 hf3 ? treq rreq type r/w reset see table 24 on page 29 icr 2k87m mask set interface control register (dma = 0, hicr = 0) 0x0 bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 hrra htra ? hf0 hf1 ? init hdm hf2 hf3 hdrq treq rreq type r/w r r/w reset see table 24 on page 29 icr 2k87m mask set interface control register (dma = 1, hicr = 0) 0x0 bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 hrra htra ? hf0 hf1 ? init hdm hf2 hf3 ? note 1 note 2 type r/w r r/w r/w reset see table 24 on page 29 notes: 1. hdm0 when read, treq when written 2. hdm0 when read, rreq when written
hdi16 functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 27 icr is a read/write control register that allows the use of bit manipulation instructions on control register bits. the host processor uses the icr to control the hdi16 interrupts and flags. the sc140 core cannot access the icr. the hpcr[dma] bit and the hcr[hicr] bit control the function of the icr bits. table 23. 2k87m mask set icr bit descriptions name description settings hrra 0?1 hdi receive request assertion the receive request is asserted a specified time based on the number of data bytes to receive. 00 hrrq asserted for 8 bytes (rx full) 01 hrrq asserted for 16 bytes (rx full + 1 hotx entry full) 10 hrrq asserted for 32 bytes (rx full + 3 hotx entries full) 11 reserved htra 2?3 hdi transmit request assertion the transmit request is asserted a specified time based on the number of data bytes to transmit. 00 htrq/hreq asserted for 8 bytes (tx empty) 01 htrq/hreq asserted for 16 bytes (tx empty + 1 hotx entry empty) 10 htrq/hreq asserted for 32 bytes (tx empty + 3 hotx entries empty) 11 reserved ? 4 reserved. write to zero for future compatibility. hf0 5 host flag 0 a general-purpose flag for host-to-core communication. the host processor can set or clear hf0. hf0 is reflected in the hsr on the core side of the hdi16. hf1 6 host flag 1 a general-purpose flag for host-to-core communication. the host processor can set or clear hf1. hf1 is reflected in the hsr on the core side of the hdi16. ? 7 reserved. write to zero for future compatibility. init 8 force initialization used by the host processor to force initialization of the hdi16 hardware (which may or may not be necessary, depending on the software design of the interface). during initialization, the hdi16 transmit and receive control bits are configured. the type of initialization performed when the init bit is set depends on the state of treq and rreq in the hdi16. the init command, which is local to the hdi16, conveniently configures the hdi16 into the desired data transfer mode. the effect of the init command is described in ta ble 25 on page 30. when the host sets the init bit, the hdi16 hardware executes the init command. the interface hardware clears the init bit after the command executes.
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 28 freescale semiconductor hdi16 hm/hdm 9?10 host mode/host dma mode when host dma mode is enabled, if hcr[hicr] is set, the hreq pin requests dma transfers, the treq and rreq bits select the direction of dma transfers, and the hack input pin is used as a dma transfer acknowledge input, if oae in hpcr is cleared. if the dma direction is from core to host, the contents of the selected register are written to the host data bus when hack is asserted. if the dma direction is from host to core, the selected register is read from the host data bus when hack is asserted. if hpcr[oae] is set, a host read or write to host address 0x4 is used as a dma transfer acknowledge. if the dma direction is from core to host, the contents of the selected register are written to the host data bus when the host reads from host address 0x4. if the dma direction is from host to core, the selected register is read from the host data bus when the host writes to host address 0x4. hm also controls the size of the dma word to be transferred. the hdi16 data register selected during a host dma transfer is determined by a 2-bit address counter, which is preloaded with the value in hm. the address counter replaces the ha[0?1] bits of the hdi16 during a host dma transfer. the address counter can be initialized with the init bit feature. after each dma transfer on the host data bus, the address counter is decremented. when the address counter reaches the last register, the address counter is loaded with the value in hm. thus, 16-bit, 32-bit, 48-bit, or 64-bit data can be transferred in a circular fashion, and the need is eliminated for the dma controller to supply the ha0?2] pins (hpcr bit oae=0) or to read/write at host address 0x4 (hpcr bit oae=1). for 32-, 48- or 64-bit data transfers, the core cpu interrupt rate is reduced by a factor of 2, 3, or 4, respectively, from the host request rate. that is, for every two or three host processor data transfers of one byte each, there is only one 64-bit core cpu interrupt. this bit is available only in icr mode (hcr[hicr] = 1). when the hdi16 is in icr priority non-dma mode (the hpcr[dma] bit is cleared and hcr[hicr] is set), data transfer size is defined by hm, as described in table 28 . the transfer size causes the rx x /tx x register read/write at the last (trigger) address to clear the rxdf/txde bits, respectively. hf2 11 host flag 2 a general-purpose flag for host-to-core communication. the host processor can set or clear hf2. hf2 is reflected in the hsr on the core side of the hdi16. hf3 12 host flag 3 a general-purpose flag for host-to-core communication. the host processor can set or clear hf3. hf3 is reflected in the hsr on the core side of the hdi16. hdrq 13 hreq/htrq and hack/hrrq pin control controls the hreq/htrq and hack/hrrq pins. if hdrq is cleared, the hreq/htrq pin functions as a single hreq. if hdrq is set, the hreq/htrq and hack/hrrq pins function as htrq and hrrq, respectively. this bit is available only in non-dma (interrupt) mode (hpcr[dma] = 0). table 23. 2k87m mask set icr bit descriptions (continued) name description settings
hdi16 functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 29 treq/hdm0 14 hreq/htreq pin control controls the hreq/htreq pin for host transmit data transfers. in non- dma (interrupt) mode (dma = 0 in the hpcr), treq enables host requests via the host request (hreq or htrq) pin when the transmit data register empty (txde) status bit in the isr is set. if treq is cleared, txde interrupts are disabled. if treq and txde are set, the host request pin is asserted. in dma modes (hpcr[dma] = 1 and hcr[hicr] = 1), software must set or clear treq to select the direction of dma transfers. setting treq sets the direction of the dma transfers as host-to-core and enables the hreq pin to request data transfers. when hcr[hicr] is cleared and hpcr[dma] is set, a treq read reflects the status of not hdm0 in hcr. when written, treq affects the init mode. see table 25 . rreq/hdm0 15 hreq and hrreq pin control controls the hreq and hrreq pins for host receive data transfers. in non-dma (interrupt) mode (hpcr[dma] = 0), rreq enables host requests via the host request (hreq or hrrq) pin when the receive data register full (rxdf) status bit in the isr is set. if rreq is cleared, isr[rxdf] interrupts are disabled. if rreq is set, the host request pin (hreq or hrrq) is asserted if isr[rxdf] is set. in host dma mode (dma = 1 in the hpcr and hicr = 1 in the hcr), rreq must be set or cleared by software to select the direction of dma transfers. setting rreq sets the direction of the host dma transfers to core-to-host and enables the hreq pin to request data transfers. when hicr in hcr is cleared and dma in hpcr is set, rreq, when read, reflects the status of hdm0 in hcr. when hcr[hicr] is cleared and hpcr[dma] is cleared, an rreq read reflects the status of hcr[hdm0]. when written, rreq affects the init mode. see table 25 . table 24. host-side registers after reset register name register data reset type hardware (hw) reset individual (ir) reset icr all bits 0 ? cvr nmi 0 0 hc 0 0 hv[0?6] 0 ? isr txde32 1 1 txde16 1 1 rxdf32 0 0 rxdf16 0 0 hreq 0 1 if treq is set; 0 otherwise hf[4?7] 0 ? trdy 1 1 txde 1 1 rxdf 0 0 rx rx[0?3] empty empty tx tx[0?3] empty empty table 23. 2k87m mask set icr bit descriptions (continued) name description settings
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 30 freescale semiconductor hdi16 ta bl e 2 5 shows the effects of the init command in relation to the values of treq and rreq. ta bl e 2 6 and ta bl e 2 7 summarize the effect of rreq and treq on the hreq and hrrq signals. ta bl e 2 8 shows the valid hm values and their meaning. 9.2 interface status register (isr) changes the following sections lists the icr layout and definitions for the 2k42a and 2k87m mask sets. table 25. effects of the init command treq rreq after init execution transfer direction initialized 0 0 init = 0 none 0 1 init = 0; isr[rxdf] = 0; hsr[htfe/htfnf] = 1 core to host 1 0 init = 0; isr[txde] = 1; hsr[hrff/hrfne] = 0 host to core 1 1 init = 0; isr[rxdf] = 0; hsr[htfe/htfnf] = 1; isr[txde] = 1; hsr[hrff/hrfne] = 0 host to/from core table 26. treq and rreq modes (hdrq = 0) in non-dma mode (hicr=1) treq rreq hreq signal 0 0 no interrupts (polling) 0 1 isr[rxdf] request (interrupt) 1 0 isr[txde] request (interrupt) 1 1 isr[rxdf] and isr[txde] request (interrupts) table 27. treq and rreq modes (hdrq = 1) in non-dma mode (hicr=1) treq rreq htrq signal hrrq signal 0 0 no interrupts (polling) no interrupts (polling) 0 1 no interrupts (polling) isr[rxdf] request (interrupt) 1 0 isr[txde] request (interrupt) no interrupts (polling) 1 1 isr[txde] request (interrupt) isr[rxdf] request (interrupt) table 28. hm host dma mode values (hicr=1) hm mode 0 1 dma mode non-dma mode 0 0 16-bit words 64-bit words. last read/write (trigger) address: 0x4 0 1 32-bit words 48-bit words. last read/write (trigger) address: 0x5 1 0 48-bit words 32-bit words. last read/write (trigger) address: 0x6 1 1 64-bit words 16-bit words. last read/write (trigger) address: 0x7
hdi16 functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 31 9.2.1 2k42a mask set isr definitions isr is a status register by which the host processor interrogates the status and flags of the hdi16. the host processor can write to this address without affecting the internal state of the hdi16. the sc140 core cannot access isr. isr 2k42a mask set interface status register 0x2 bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ? hreq hf4 hf5 hf6 hf7 trdy txde rxdf type r reset see table 24, ?host-side registers after reset,? on page 29 table 29. 2k42a mask set isr bit descriptions name description settings ? 0?7 reserved. write to zero for future compatibility. hreq 8 hreq status hreq indicates the status of the external transmit and receive request output signals (htrq and hrrq) if hdrq is set. if hdrq is cleared, it indicates the status of the external host request output signal (hreq). the hreq bit can be set under either or both of two conditions: the receive word registers (rx[0?3]) are full or the transmit word registers (tx[0?3]) are empty. these conditions are indicated by the isr rxdf and txde status bits, respectively. if the interrupt source has been enabled by the associated request enable bit in the icr, hreq is set if one or more of the two enabled interrupt sources is set. if hdrq is cleared: 0 no host processor interrupts requested. 1 interrupt requested. if hdrq is set: 0 no host processor interrupts requested (htrq and hrrq cleared). 1 interrupt requested (htrq or hrrq set). hf[4?7] 9?12 host flags 4?7 indicates the state of host flags 4 ? 7 in the hcr on the core side. only the sc140 core can change hf[4 ? 7]. trdy 13 trdy status indicates whether the transmit word registers tx[0 ? 3] and the horx fifo are empty. trdy is set if txde is set and hrfne is cleared. if trdy is set, the data that the host processor writes to tx[0 ? 3] is immediately transferred to the core side of the hdi16 and can be read by the sc140 core. this feature has many applications. for example, if the host processor issues a host command that causes the sc140 core to read horx, the host processor can be certain that the data it just transferred to the hdi16 is the same data received by the sc140 core. 0tx[0 ? 3] and the horx fifo are not empty. 1 tx[0?3] and the horx fifo are empty. txde 14 transmit data empty indicates whether the transmit word registers (tx[0 ? 3]) are empty and can be written by the host processor. txde is set when the contents of the tx[0 ? 3] registers are transferred to the horx register. txde is cleared when the host processor writes to the transmit data registers (tx) and the horx fifo is full. the host processor sets txde using the initialize function. txde can assert the external hreq/htrq signal if the treq bit is set. regardless of whether the txde interrupt is enabled, txde indicates whether the tx registers are full and data can be latched in so that the host processor can use polling techniques. 0 the tx registers are not empty. 1 the tx registers are empty and can be written by the host processor.
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 32 freescale semiconductor hdi16 9.2.2 2k87m mask set isr definitions isr is a status register by which the host processor interrogates the status and flags of the hdi16. the host processor can write to this address without affecting the internal state of the hdi16. the sc140 core cannot access isr. rxdf 15 receive data full indicates whether the receive word registers (rx[0 ? 3]) contain data from the sc140 core and can be read by the host processor. rxdf is set when the hotx is transferred to the rx[0 ? 3] registers. rxdf is cleared when the host processor reads the receive data registers (rx) at the last address and the hotx fifo is empty. the host processor can clear rxdf using the initialize function. rxdf can be used to assert the external hreq/hrrq signal if rreq is set. regardless of whether the rxdf interrupt is enabled, rxdf indicates whether the rx registers are full and data can be latched out, so that the host processor can use polling techniques. 0 the rx registers are not full. 1 the rx registers are full and can be read by the host processor. isr 2k87m mask set interface status register 0x2 bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ? txde3 2 txde1 6 rxdf3 2 rxdf1 6 hreq hf4 hf5 hf6 hf7 trdy txde rxdf type r reset see table 30 table 30. 2k87m mask set isr bit descriptions name description settings ? 0?3 reserved. write to zero for future compatibility. txde32 4 transmit queue 32 bytes empty 0 < 32 bytes are empty 1 32 bytes are empty (24 bytes in horx and 8 bytes in tx) txde16 5 transmit queue 16 bytes empty 0 < 16 bytes are empty 1 16 bytes are empty (8 bytes in horx and 8 bytes in tx) rxdf32 6 receive queue 32 bytes full 0 < 32 bytes are full 1 32 bytes are full (24 bytes in hotx and 8 bytes in rx) rxdf16 7 receive queue 16 bytes full 0 < 16 bytes are full 1 16 bytes are full (8 bytes in hotx and 8 bytes in rx) table 29. 2k42a mask set isr bit descriptions (continued) name description settings
hdi16 functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 33 hreq 8 hreq status hreq indicates the status of the external transmit and receive request output signals (htrq and hrrq) if hdrq is set. if hdrq is cleared, it indicates the status of the external host request output signal (hreq). the hreq bit can be set under either or both of two conditions: the receive word registers (rx[0?3]) are full or the transmit word registers (tx[0?3]) are empty. these conditions are indicated by the isr rxdf and txde status bits, respectively. if the interrupt source has been enabled by the associated request enable bit in the icr, hreq is set if one or more of the two enabled interrupt sources is set. if hdrq is cleared: 0 no host processor interrupts requested. 1 interrupt requested. if hdrq is set: 0 no host processor interrupts requested (htrq and hrrq cleared). 1 interrupt requested (htrq or hrrq set). hf[4?7] 9?12 host flags 4?7 indicates the state of host flags 4 ? 7 in the hcr on the core side. only the sc140 core can change hf[4 ? 7]. trdy 13 trdy status indicates whether the transmit word registers tx[0 ? 3] and the horx fifo are empty. trdy is set if txde is set and hrfne is cleared. if trdy is set, the data that the host processor writes to tx[0 ? 3] is immediately transferred to the core side of the hdi16 and can be read by the sc140 core. this feature has many applications. for example, if the host processor issues a host command that causes the sc140 core to read horx, the host processor can be certain that the data it just transferred to the hdi16 is the same data received by the sc140 core. 0tx[0 ? 3] and the horx fifo are not empty. 1 tx[0?3] and the horx fifo are empty. txde 14 transmit data empty indicates whether the transmit word registers (tx[0 ? 3]) are empty and can be written by the host processor. txde is set when the contents of the tx[0 ? 3] registers are transferred to the horx register. txde is cleared when the host processor writes to the transmit data registers (tx) and the horx fifo is full. the host processor sets txde using the initialize function. txde can assert the external hreq/htrq signal if the treq bit is set. regardless of whether the txde interrupt is enabled, txde indicates whether the tx registers are full and data can be latched in so that the host processor can use polling techniques. 0 the tx registers are not empty. 1 the tx registers are empty and can be written by the host processor. rxdf 15 receive data full indicates whether the receive word registers (rx[0 ? 3]) contain data from the sc140 core and can be read by the host processor. rxdf is set when the hotx is transferred to the rx[0 ? 3] registers. rxdf is cleared when the host processor reads the receive data registers (rx) at the last address and the hotx fifo is empty. the host processor can clear rxdf using the initialize function. rxdf can be used to assert the external hreq/hrrq signal if rreq is set. regardless of whether the rxdf interrupt is enabled, rxdf indicates whether the rx registers are full and data can be latched out, so that the host processor can use polling techniques. 0 the rx registers are not full. 1 the rx registers are full and can be read by the host processor. note: a status bit is set when there are a number of empty/full bytes more than the status bit indicates. for example, if there are 3 2 empty bytes, all three relevant status bits (txde32, txde16, and txde) are set. table 30. 2k87m mask set isr bit descriptions (continued) name description settings
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 34 freescale semiconductor hdi16 9.3 hreq logic differences the following sections describe the implementation of hreq logic for the 2k42a and 2k87m mask sets. 9.3.1 2k42a mask set hreq logic when hreq is connected to the host processor interrupt input, the hdi16 asserts hreq to request service from the host processor. hreq is asserted when txde is set and/or isr[rxdf] is set, and the corresponding enable bit (treq or rreq, respectively) is set, as figure 9 shows. the host processor acknowledges host interrupts by executing an interrupt service routine. the host processor tests isr[rxdf] and isr[txde] to determine the interrupt source. the host processor interrupt service routine must read or write the appropriate hdi16 data register to clear the interrupt. hreq is deasserted under the following conditions: the enabled request is cleared or masked. the sc140 core is reset. 9.3.2 2k87m mask set hreq logic when hreq is connected to the host processor interrupt input, the hdi16 asserts hreq to request service from the host processor. hreq is asserted according to the programming of icr[htra] and the status bits txde, txde16, and txde2 when icr[treq] is set, or according to the programming of icr[hrra] and the status bits rxdf, rxdf16, and rxdf32 when icr[rreq] is set, as figure 10 shows. the programming of hrra or htra chooses the status bit, and depending on its value, hreq is asserted or deasserted. figure 9. hdi16 host request structure treq rreq icr enable 815 init status 8 15 trdy txde rxdf isr hreq host request asserted hrrq hreq htrq
hdi16 functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 35 the host processor acknowledges host interrupts by executing an interrupt service routine. the host processor tests the appropriate status bit (txde, txde16, txde32, rxdf, rxdf16, or rxdf32, depending on the application) to determine the interrupt source. the host processor interrupt service routine must read or write the appropriate hdi16 data register to clear the interrupt. hreq is deasserted under the following conditions: the enabled request is cleared or masked. the sc140 core is reset. figure 10. hdi16 host request structure treq rreq icr[8?15] 815 init 8 15 trdy txde rxdf isr[8?15] hreq host request asserted hreq icr[0?7] 01 01 hrra htra isr[0?7] rxdf16 htrq hrrq txde32txde16 rxdf32
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 36 freescale semiconductor dma transfer code definitions 10 dma transfer code definitions the tc code definitions for mask sets 2k42a and 2k87m are as follows: 11 interrupt system 11.1 scprr_l and scprr_l_ext changes for mask set 2k87m, the tc layer interrupts are configured with the sccs using the ycc entries defined by the cpm low interrupt priority registers (scprr_l and scprr_l_ext). for the fields yc1p?yc8p in each register, the value 100 (which was reserved for mask set 2k42a) is reassigned to ?tc layer asserts its request in the yccn position.? 11.2 tc layer interrupts the tc layer accesses use interrupt vector 44 (this was reserved for mask set 2k42a). 12 debugging 12.1 jtag id changes the jtag id value for the 2k42a mask set is 0x0188201d. the jtag id value for the 2k87m mask set is 0x1188201d. 12.2 eonce status register (esr) values for the 2k42a mask set, esr[revno] = 1 and esr[coretp] =1. for the 2k87m mask, esr[revno] = 2 and esr[coretp] = 2. 12.3 eonce counter register values for the 2k42a mask set, the event counter value register (ecnt_val) and the extension counter value register (ecnt_ext) have a maximum value of 0xffffffff. for the 2k87m mask set, the most significant bit (msb) of these registers is hard-wired to 0, limiting the maximum register value to 0x7fffffff. when reading either register, the msb is always zero. for future compatibility, always write a 0 to the msb of these registers. table 31. transfer code encoding tc[0?2] 2k42a 2k87m 000 reserved reserved 001 reserved reserved 010 reserved reserved 011 reserved reserved 100 reserved dma function code 0 101 sc140 core sc140 core/dma function code 1 110 sdma/dma function code 0 sdma 111 sdma/dma function code 1 sdma
efcop functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 37 note: when the counter value is written to the trace buffer, it is shifted one position to the left so the debugger can use the least significant bit (lsb) to identify a new entry in the trace buffer. 13 efcop the msc8103 mask set 2k87m does not support an efcop module. 14 cpm the 2k87m cpm adds functionality. the contents of the risc controller configuration register (rccr) changed to accommodate the increased size of the dual-port ram. support for a rom-based inverse multiplexing for atm (ima) microcode was added. transmission convergence (tc) layer functionality required to support ima was added to the time-slot assigner (tsa). also, new mcc host commands are added. the following sections discuss these changes. 14.1 risc controller configurat ion register (rccr) changes the 2k87m mask set risc controller configuration (rccr) expands the enable ram microcode (eram) field from 3 to 4 bits wide (adding rccr to 19 bit which was reserved in the 2k42a mask set) to reflect the availability of dual-port ram space starting at address 0x4000. rccr 2k87m mask set risc controller configuration register 0x119c4 bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 time ? timep ext[ 1?2] m 1 ext 1 p 1 ? scd ext 2 p 1 type r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit16171819202122232425262728293031 eram edm [1?4] 1 ext[ 3?4] m 1 ext 3 p 1 ? ext 4 p 1 type r/w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 notes: 1. reserved for future microcode applications
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 38 freescale semiconductor cpm rccr configures the cp to run microcode from rom or ram and controls the cp internal timer. table 32. 2k87m mask set rccr bit descriptions name reset description settings time 0 0 timer enable enables the cp internal timer that generates a tick to the cp based on the value programmed into the timep field. time can be modified at any time to start or stop the scanning of the risc timer tables. 0 timer disabled 1 timer enabled ? 1 0 reserved. write to zero for future compatibility. timep 2?7 0 timer period controls the cp timer tick. the risc timer tables are scanned on each timer tick, and the input to the timer tick generator is the general system clock (150 mhz) divided by 1,024. the formula is (timep + 1) 1,024 = (general system clock period). thus, a value of 0 stored in these bits gives a timer tick of 1 (1,024) = 1,024 general system clocks and a value of 63 (decimal) gives a timer tick of 64 (1,024) = 65,536 general system clocks. ext [1?2] m 8?9 0 external request mode controls the external request sensitivity note: reserved for future microcode applications. 0 ext x is edge sensitive according to edmx 1 ext x is level sensitive according to edmx ext1p 10?11 0 external request priority controls the external request priority relative to communication controllers note: reserved for future microcode applications. 00 ext x has higher priority than the communication controllers (default) 01 ext x has lower priority than the communications controllers 10 ext x has the lowest priority 11 reserved ? 12 0 reserved. write to zero for future compatibility. scd 13 0 scheduler configuration configure as instructed in the download process of a freescale-supplied ram microcode package. 0 normal operation 1 alternate configuration of the scheduler ext2p 14?15 0 external request priority controls the external request priority relative to communication controllers note: reserved for future microcode applications. 00 ext x has higher priority than the communication controllers (default) 01 ext x has lower priority than the communications controllers 10 ext x has the lowest priority 11 reserved
cpm functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 39 eram 16?19 0 enable ram microcode configure as instructed in the download process of a freescale-supplied ram microcode package. note : this area was expanded from the 3-bit field used by the 2k42a mask set. edm[1?4] 20?23 0 edge detect mode ext x asserts requests according to settings note: reserved for future microcode applications. 0 low to high change for ext x = 0, active high for ext x = 1 1 high to low change for ext x = 0, active low for ext x = 1 ext[3?4]m 24?25 0 external request mode controls the external request sensitivity note: reserved for future microcode applications. 0 ext x is edge-sensitive according to edmx 1 ext x is level-sensitive according to edmx ext3p 26?27 0 external request priority controls the external request priority relative to communication controllers note: reserved for future microcode applications. 00 ext x has higher priority than the communication ?controllers (default) 01 ext x has lower priority than the communications controllers 10 ext x has the lowest priority 11 reserved ? 28?29 0 reserved for future applications table 32. 2k87m mask set rccr bit descriptions (continued) name reset description settings eram ram microcode 0000 disable microcode program execution from the dual-port ram. for the following, execution starts at 0x0000 after reset: 0010 microcode uses the first 2 kb + 8 kb from 0x4000 0100 microcode uses the first 4 kb + 8 kb from 0x4000 0110 microcode uses the first 6 kb + 8 kb from 0x4000 1000 microcode uses the first 8 kb + 8 kb from 0x4000 1010 microcode uses the first 10 kb + 8 kb from 0x4000 1100 microcode uses the first 12 kb + 8 kb from 0x4000 for the following, execution starts at 0x4000 after reset: 0011 microcode uses the first 2 kb starting from 0x4000 0101 microcode uses the first 4 kb starting from 0x4000 0111 microcode uses the first 6 kb starting from 0x4000 1001 microcode uses the first 8 kb starting from 0x4000 all other combinations are reserved.
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 40 freescale semiconductor cpm 14.2 dual-port ram change the dual-port ram has been expanded to 32 kb of static ram. an extra 8 kb starting at address 0x4000 is available for microcode execution only and cannot be used for data buffers or bds. however, when not used for microcode, the extra 8 kb can be accessed from the system bus for general purpose internal storage. 14.2.1 2k42a mask set 24 kb dual-port ram memory map figure 11 shows the msc8101 2k42a mask set memory map of the dual-port ram. ext4p 30?31 0 external request priority controls the external request priority relative to communication controllers note: reserved for future microcode applications. 00 ext x has higher priority than the communication controllers (default) 01 ext x has lower priority than the communications controllers 10 ext x has the lowest priority 11 reserved figure 11. 2k42a mask set 24 kb dual-port ram memory map table 32. 2k87m mask set rccr bit descriptions (continued) name reset description settings bd/data/code 2 kb bank 1 0x0000 bd/data/code 2 kb bank 2 0x0800 bd/data/code 2 kb bank 3 0x1000 bd/data/code 2 kb bank 4 0x1800 bd/data/code 2 kb bank 5 0x2000 bd/data/code 2 kb bank 6 0x2800 bd/data 2 kb bank 7 0x3000 bd/data 2 kb bank 8 0x3800 bd/data/code 2 kb bank #1 0x4000 bd/data/code 2 kb bank #1 bd/data/code 2 kb bank #1 bd/data/code 2 kb bank #1 bd/data/code 2 kb bank #1 bd/data/code 2 kb bank #1 bd/data/code 2 kb bank #1 bd/data/code 2 kb bank #1 parameter ram 2 kb bank 9 0x8000 parameter ram 2 kb bank 10 0x8800 bd/data/code 2 kb bank #11 0x9000 bd/data/code 2 kb bank #1 bd/data/code 2 kb bank #1 bd/data/code 2 kb bank #1 fcc data 2 kb bank 11 0xb000 fcc data 2 kb bank 12 0xb800 reserved reserved (partially reserved)
cpm functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 41 14.2.2 2k87m mask set dual-port ram memory map figure 12 shows the msc8103 2k87m mask set memory map of the dual-port ram. 14.3 ima functionality ima functionality is similar to the updated functionality described in mpc8266aumad/d for updates to the mpc826x product family. this document can be accessed from the freescale website listed on the back page of this document. 14.4 tsa changes the 2k87m mask set adds functionality required to support the new atm transmission convergence (tc) layer added to the communications processor module (cpm) in the time-slot assigner (tsa). this functionality can only be configured and used by the fast communications controller 2 (fcc2) for atm interfaces using the ima functionality. figure 12. 2k87m mask set 32 kb dual-port ram memory map bd/data/code 2 kb bank #1 0x0000 bd/data/code 2 kb bank #2 0x0800 bd/data/code 2 kb bank #3 0x1000 bd/data/code 2 kb bank #4 0x1800 bd/data/code 2 kb bank #5 0x2000 bd/data/code 2 kb bank #6 0x2800 bd/data 2 kb bank #7 0x3000 bd/data 2 kb bank #8 0x3800 parameter ram 2 kb bank #9 0x8000 parameter ram 2 kb bank #10 0x8800 bd/data/code 2 kb bank #11 0x9000 bd/data/code 2 kb bank #1 bd/data/code 2 kb bank #1 bd/data/code 2 kb bank #1 fcc data 2 kb bank #11 0xb000 fcc data 2 kb bank #12 0xb800 reserved (partially reserved) microcode 2 kb bank #13 0x4000 microcode 2 kb bank #14 0x4800 microcode 2 kb bank #15 0x5000 microcode 2 kb bank #16 0x5800 0x6000 reserved
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 42 freescale semiconductor cpm 14.4.1 tc layer functionary figure 13 shows a block diagram of the si blocks and tsa.the tsa also contains transmission convergence (tc) layer hardware. note: tc layer support for atm (fcc2 only) with tc layer 1 supported through tdma1 and tc layers 6?8 supported through tdmb2, tdmc2, and tdmd2, respectively. for the fcc2 atm utopia 8, the si supports the following: four tdm channels routed in hardware to a tc layer block protocol-specific overhead bits may be discarded or routed to other controllers by the si performing atm tc layer functions (according to itu-t i.432) transmit (tx) updates include: ? cell hec generation ? payload scrambling using self synchronizing scrambler (programmable by the user) ? coset generation (programmable by the user) ? cell rate by inserting idle/unassigned cells receive (rx) updates include: ? cell delineation using bit by bit hec checking and programmable alpha and delta parameters for the figure 13. si block diagram time-slot assigner (tsa) r clocks t clocks r clocks t clocks r sync t sync tdma, b, c, d pins strobes route si ram tx/rx ram control mode register tdma, b, c, d tx tx command register status register smc1 smc2 scc1 scc2 mii1/ mii2 mux to: smc1 smc2 scc1 scc2 scc3 scc4 fcc1 fcc2 fcc3 multi-channel peripheral bus non-multiplexed serial interface (nmsi) pins channel # controllers shadow register clock route ram address rx rx utopia cpm mux note: the cpm multiplexer and the mccs are not part of the si. mux mux mux mux mux mux mux mux (mccs) (see chapters 22 and 33 for details.) tc layer hardware (fcc2 only)
cpm functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 43 delineation state machine ? payload descrambling using self synchronizing scrambler (programmable by the user) ? coset removing (programmable by the user) ? filtering idle/unassigned cells (programmable by the user) ? performing hec error detection and single bit error correction (programmable by the user) ? generating loss of cell delineation status/interrupt (loc / lcd) serial loop back mode cell echo mode supports both fcc transmit modes: ? external rate mode?idle cells are generated by the fcc (microcode) to control data rate ? internal rate mode (sub-rate)?fcc transfers only the data cells using the required data rate. the tc layer generates idle/unassigned cells to maintain the line bit rate supports the tc layer and pmd (physical medium dependant) wire interface (according to the atm-forum af-phy-0063.000) 14.4.2 atm tc layer support the msc8103 supports applications that receive atm traffic over the standard serial protocols like e1, t1, and xdsl via its serial interface (six tdmx and nmsi) ports because the atm tc-layer functionality is implemented internally. this allows the use of standard low-cost phy devices in system applications instead of phys that support utopia bus devices. a typical tc layer application requires the use of one si tdm channel per tc block. as shown in figure 14 , all tc blocks are internally connected to fcc2. in addition, figure 14 shows fcc1 connected to a utopia 8-bit mphy bus that can be routed outside and operated independently from the tc block figure 14. serial atm interface using fcc2 and tc blocks (single channel) fcc2 fcc1 utopia level-2 8-bit bus dpr tdmx fcc3 tc six utopia level-2 8-bit bus blocks
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 44 freescale semiconductor cpm 14.4.3 tc layer support the tc layer block is shown in figure 15 . the transmit and the receive parts are independent; the only case in which they are synchronized is in cell echo mode. 14.4.4 signals the tc layer operates via an si tdm port or nmsi port using a serial protocol. synchronization signals are required for some applications and must be supported. table 33 describes the signals for operating the tc layer. figure 15. tc layer block diagram table 33. tc layer signals signal direction description txc input transmit clock. clocks tx data out of the tc to external device. txd output transmit data from tc to external device. tx sync input transmit synch. synchronizes the transmit data to the beginning of a frame. rxc input receive clock. clocks the data into the tc. rxd input receive data. from external device to the tc. rx sync input receive synch. synchronizes the received data. not required in nmsi mode. si powerquicc ii tc layer phy rx cell functions cell delineation descrambling coset hec error correction tx utopia i/f rx utopia i/f (phy) (phy) tx serial i/f rx serial i/f counters registers fcc2 one channel rx tx dbb bus utopia rx i/f utopia tx i/f m-phy m-phy detection and rx fifo tx fifo tx cell functions hec generation scrambling coset rate adaptation
cpm functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 45 14.4.5 receive atm cell functions the atm receive cell functions block (rcf) performs the receive functions of the tc block. it performs cell delineation, cell payload descrambling, hec verification and correction, and idle/unassigned cell filtering. cell delineation is the process of framing data to atm cell boundaries using the header error check (hec) received in the atm cell header. the hec is a crc-8 calculation over the first four octets of the atm cell header. the cell delineation algorithm assumes that repetitive correct hec calculations over consecutive cells indicate valid atm cell boundaries. the rcf performs a sequential bit-by-bit hunt for a correct hec sequence, and the cell delineation state machine is in hunt state. when a correct hec is found, the rcf locks on the particular cell boundary and enters the presynch state, which indicates that the previously detected hec pattern is not a false indication. if a correct hec pattern is false, an incorrect hec is received within the next delta cells. if an incorrect cell is detected, there is a transition to the hunt state. if an incorrect hec is not detected in the presynch state, there is a transition to the synch state. in the synch state, the tc is assumed to be synchronized so that other functions can be applied to the received cell. a transition back to the hunt state is made only after alpha consecutive incorrect hec patterns are detected. the cell delineation state machine is shown in figure 16 . the alpha and delta parameters determine the robustness of the delineation method. alpha determines the robustness against false misalignment due to bit errors. delta determines the robustness against false delineation in the synchronization. both parameters are programmable for each tc block and are provided to help tune the system according to the line error characteristics of a specific application. the rcf descrambles (programmable) the cell payload using the self-synchronizing descrambler with a polynomial of x 43 + 1. the hec calculation is a crc-8 calculation over the first four octets of the atm cell header. the rcf verifies the received hec using the accumulation polynomial, x 8 + x 2 + x + 1. the coset polynomial x 6 +x 4 + x 2 + 1 is added (modulo 2) to the received hec octet before comparison with the calculated result (programmable). figure 16. tc cell delineation state machine hunt presynch synch delta consecutive correct hec correct hec incorrect hec alpha incorrect hec consecutive bit-by-bit cell-by-cell cell-by-cell
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 46 freescale semiconductor cpm the rcf can perform single bit error correction on the header. if multiple bit errors are found in the hec, the cell is discarded. if the single bit error correction mode is not enabled (tcmode[sbc] = 1), the cell is also discarded when a single bit error is found in the header. when the cell delineation state machine is in the synch state, the hec verification state machine (see figure 17 ) implements the correction algorithm. this state machine ensures that a single cell header is corrected at a time. if consecutive cells are detected with single bit errors in their headers, only the first cell error is corrected and the rest are discarded. this state machine reduces the delivery of cells with headers containing errors under bursty error conditions. the rcf can also perform idle/unassigned cell filtering. both features are programmable (tcmode[cf]). cells that are detected to be idle/unassigned are discarded, that is, not forwarded to the utopia interface rx fifo. 14.4.6 receive atm 2-cell fifo the receive fifo provides fifo management and an interface to the utopia receive cell interface. the receive fifo can hold 2 atm cells, thereby providing the cell rate decoupling function between the transmission system physical layer and the atm layer. fifo management includes filling the fifo, indicating to the utopia interface that it contains cells, maintaining the fifo read and write pointers, and detecting fifo overrun (tcer[or]) conditions. 14.4.7 transmit atm cell functions the transmit atm cell functions block (tcf) performs the atm cell payload scrambling and is responsible for the hec generation and the idle/unassigned cell generation. the tcf scrambles (programmable by the user) the cell payload using the self-synchronizing scrambler with polynomial x 43 + 1. the hec is generated using the polynomial x 8 + x 2 + x + 1. the coset polynomial x 6 +x 4 + x 2 + 1 is added (modulo 2) (programmable by the user) to the calculated hec octet. the result overwrites the hec octet on the transmitted cell. when the transmit fifo is empty, the tcf inserts idle/unassigned cells (counted in icc). the tcf accumulates the number of transmitted assigned cells in a counter (tcc). 14.4.8 transmit atm 2-cell fifo the transmit fifo provides fifo management and an interface to the utopia transmit interface. the fifo provides the cell rate decoupling between the transmission system physical layer and the atm layer. figure 17. hec: receiver modes of operation detection correction multi-bit error mode mode detected (cell discarded) no error detected (correction) single-bit error detected error detected (cell discarded) no error detected (no action)
cpm functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 47 the fifo management includes emptying cells from the transmit fifo, indicating to the utopia interface that it is full, maintaining the fifo read and write pointers, and detecting fifo underrun (tcer[ur]) conditions. 14.4.9 rx utopia interface t he receive interface with the fcc via the utopia bus implements the utopia level-2 (multi-phy) 8-bit pmd side (slave) interface. 14.4.10 tx utopia interface t he transmit interface with the fcc via the utopia bus implements the utopia level-2 (multi-phy) 8-bit pmd side (slave) interface. 14.4.11 tc layer registers each tc layer block is controlled by registers in the block and accessed from the 60x-compatible bus. 14.4.12 tc layer mode register (tcmode) each tc layer block is configured using a tc layer mode register tcmodex, as shown in figure 18 . ta bl e 3 4 describes tcmode fields. bit0123456789101112131415 field rxen txen rps tps rc tc sbc cf ure lb tba ima sm cm reset0000000000000000 r/w r/w figure 18. tcmodex table 34. tcmode field descriptions name description settings rxen 0 tc layer receive enable enables the tc layer rx block operation 0 tc layer rx operation disabled 1 tc layer rx operation enabled txen 1 tc layer transmit enable enables the tc layer tx block operation 0 tc layer tx operation disabled 1 tc layer tx operation enabled rps 2 receive payload descrambling disable disables payload descrambling on received payload data 0 received payload descrambling 1 no received payload descrambling tps 3 transmit payload scrambling disable disables payload scrambling on transmitted payload data 0 transmit payload scrambling 1 no transmit payload scrambling rc 4 receive coset disable disables xor with 0xaa on received hec 0 xor with 0xaa on received hec 1 no xor with 0xaa on received hec tc 5 transmit coset disable disables xor with 0xaa on transmitted hec 0 xor with 0xaa on transmitted hec 1 no xor with 0xaa i on transmitted hec sbc 6 header single bit error correction disable disables single bit correction on the header according to hec in sync mode. 0 single bit error correction 1 no single bit error correction
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 48 freescale semiconductor cpm 14.4.13 cell delineation state machine register (cdsmrx) the cell delineation state machine register (cdsmr), shown in figure 19 , holds the alpha and delta parameters of the cell delineation state machine. ta bl e 3 5 describes the cdsmr fields. cf 7?8 receive idle/unassigned cells filtering selects the type of filtering to perform on received cells. the header of an idle cell (itu-t i.361) is 0b00000000_00000000_00000000_00000001. the header of an unassigned cell (itu-t i.361) is 0b00000000_00000000_00000000_0000xxx0 physical layer cells bypass the tc layer; they are not filtered. the filter works on the header only and ignores the hec. 00 no cell filtering is done on rx cells. 01 idle cell filtering is done and idle cells are discarded. 10 unassigned cell filtering is done and unassigned cells are discarded. 11 idle and unassigned cell filtering is done and both idle and unassigned cells are discarded. ure 9 underrun interrupt (tcer[ur]) enable an underrun interrupt may be set when an idle cell is generated by the tc. 0 underrun interrupt disabled 1 underrun interrupt enabled lb 10?11 loopback/echo modes for echo mode operation, clear tcmode[sm], independent of the fcc multi- phy mode configuration. 00 normal operation. 01 cell echo mode operation. received cells are transmitted and do not go out to the utopia bus. 10 data loopback mode operation. transmit data stream is connected to the receive data stream. 11 not used. tba 12 transmit byte align enables alignment of transferred bytes to the tx sync signal. 0 tx data is transferred as soon as it is enabled 1 tx data is transferred byte-aligned to the tx sync signal ima 13 ima mode enables ima mode. 0 rx is not in ima 1 rx is in ima mode sm 14 single mode indicates whether the tc is the only phy on the utopia interface. 0 tc is not the only phy on utopia 1 tc is the only phy on utopia cm 15 cell counters mode disables the counter read and then clear function. 0 reading a cell counter clears the counter 1 reading a cell counter does not change the counter value bit0123456789101112131415 field alpha delta ? reset0000000000000000 r/w r/w figure 19. cdsmrx table 35. cdsmr field descriptions name description alpha 0-4 alpha consecutive received cells with incorrect hec are counted by the cell delineation state machine to pass from state synch to state hunt. delta 5-9 delta consecutive received cells with correct hec are counted by the cell delineation state machine to pass from state presynch to state synch. ? 10?15 reserved. write to 0 for future compatibility. table 34. tcmode field descriptions (continued) name description settings
cpm functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 49 14.4.14 tc layer event register (tcerx) the tc layer event registers (tcerx), as shown in figure 20 , records error events for each tc block. tcer event bits are cleared by writing ones to them. the tcer bits are described in ta bl e 3 6 . 14.4.15 tc layer mask register (tcmrx) the tcmrx field description is identical to that of tcer (refer to section 14.4.14 ). each bit that is set in tcmr enables an interrupt when the corresponding bit in tcer is set. bit0123456789101112131415 field or ur cdt ms pare ? rof tof eof cof iof fof reset0000000000000000 r/w r/w figure 20. tcerx table 36. tcer field descriptions name description description or 0 overrun indicates whether the rx fifo is full when a complete cell is received. 0 the rx fifo is not full or another complete cell is not received. 1 the rx fifo is full and another complete cell is received. the cell is discarded. ur 1 underrun indicates whether there is no atm cell to transmit. the interrupt is enabled only if tcmode[ure] is set. 0 the tx fifo is not empty or the cell transmission is not completed. 1 the tx fifo is empty and the cell transmission is completed. an idle cell is sent. the idle cell header is 0x00000001 (i.432), whose hec is 0x52. the idle cell payload is 0x6a (i.432). cdt 2 cell delineation toggled indicates whether the cell delineation bit (tcgsr[cd]) bit changed. 0 tcgsr[cd] did not change. 1 tcgsr[cd] changed. ms 3 misplaced tx sync signal indicates whether the tx sync is out of place. the first tx sync is by definition always in place. 0 tx sync is not out of place. 1 tx sync is out of place. pare 4 parity event indicates whether the parity is incorrect. 0 the transmit parity from utopia is correct. 1 the transmit parity from utopia is wrong. ? 5?9 reserved. write to 0 for future compatibility. rof 10 received cell counter overflow indicates that the received cells counter passed its maximum value. 0 the received cells counter did not pass its maximum value. 1 the received cells counter passed its maximum value. tof 11 transmitted cell counter overflow indicates that the transmitted cells counter passed its maximum value. 0 the transmitted cells counter did not pass its maximum value. 1 the transmitted cells counter passed its maximum value. eof 12 errorred cells counter overflow indicates that the errorred cells counter passed its maximum value. 0 the errored cells counter did not pass its maximum value. 1 the errored cells counter passed its maximum value. cof 13 corrected cells counter overflow indicates that the corrected cells counter passed its maximum value. 0 the corrected cells counter did not pass its maximum value. 1 the corrected cells counter passes its maximum value. iof 14 tx idle cells counter overflow indicates that the tx idle cells counter passed it maximum value. 0 the tx idle cells counter did not pass its maximum value. 1 the tx idle cells counter passes its maximum value. fof 15 filtered cells counter overflow indicates that the filtered cells counter passed its maximum value. 0 the filtered cells counter did not pass its maximum value. 1 the filtered cells counter passed its maximum value.
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 50 freescale semiconductor cpm 14.4.16 tc layer general registers the tc layer general registers are distributed to all of the tc blocks. each tc block is represented by specific bits. when accessing a general register, each tc block is responsible only for its bits. 14.4.17 tc layer general event register (tcger) the tc layer general event register (tcger), shown in figure 21 , summarizes the events for all the tc blocks. each bit stands for an ored event register of a tc block. when a bit is set, it indicates that one or more event bits are set in the corresponding tc block event register. ta bl e 3 7 describes tcger fields. 14.4.18 tc layer general status register (tcgsr) figure 22 shows the tc layer general status register (tcgsr), which records the cell delineation and transmit fifo status for all tc blocks. bit0123456789101112131415 field tc1 ? tc6 tc7 tc8 ? reset0000000000000000 r/w r/w figure 21. tcger table 37. tcger field descriptions name description settings tc1 0 tc1 event indicates whether a tc layer 1 event occurred. 0 no event. 1 one or more bits are set in tc1 event register. ? 1?4 reserved. write to 0 for future compatibility. tc6 0 tc6 event indicates whether a tc layer 6 event occurred. 0 no event. 1 one or more bits are set in tc6 event register. tc7 0 tc7 event indicates whether a tc layer 7 event occurred. 0 no event. 1 one or more bits are set in tc7 event register. tc8 0 tc8 event indicates whether a tc layer 8 event occurred. 0 no event. 1 one or more bits are set in tc8 event register. ? 8?15 reserved. write to 0 for future compatibility. bit0123456789101112131415 field cd1 ? cd6 cd7 cd8 ? reset0000000000000000 r/w r figure 22. tcgsr
cpm functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 51 ta bl e 3 8 describes tcgsr fields. 14.4.19 tc layer cell counters each tc block maintains six memory-mapped 16-bit performance cell counters listed in ta bl e 3 9 that are updated during operation and can be read by the host. if a counter overflows, it wraps back to zero and generates a maskable interrupt. these counters are automatically cleared when read if tcmode[cm] = 0; see section 14.4.12 . 14.4.20 programming fcc2 fcc2 is designed to work with the tc blocks. the tc blocks are located on fixed addresses on the utopia bus internally. fcc2 should be programmed to work with the tc blocks as if the tc blocks are external phys located on the lowest eight (or fewer) addresses. table 38. tcgsr field descriptions name description settings cd1 0 cell delineation the cell delineation state machine status of tc1. 0 cell delineation state machine is in hunt or pre-synch mode. 1 cell delineation machine is in synch mode. ? 1?4 reserved. write to 0 for future compatibility. cd6 0 cell delineation the cell delineation state machine status of tc6. 0 cell delineation state machine is in hunt or pre-synch mode. 1 cell delineation machine is in synch mode. cd7 0 cell delineation the cell delineation state machine status of tc7. 0 cell delineation state machine is in hunt or pre-synch mode. 1 cell delineation machine is in synch mode. cd8 0 cell delineation the cell delineation state machine status of tc8. 0 cell delineation state machine is in hunt or pre-synch mode. 1 cell delineation machine is in synch mode. 8?15 reserved. write to 0 for future compatibility. table 39. tc performance cell counters counter name description received cell counter (rcc) this cell counter is updated whenever a received cell without hec errors is passed to the rx utopia fifo. transmitted cell counter (tcc) this cell counter is updated whenever the transmission of a cell is completed. errored cell counter (ecc) this cell counter is updated whenever a received errored cell (cell with header error) is discarded. corrected cell counter (ccc) this cell counter is updated whenever a received cell with a hec single bit error is corrected. if header single bit error correction is not enabled (tcmode[sbc] is set), this counter is not updated. (all errored cells are counted by the errored cell counter (ecc).) tx idle cell counter (icc) this cell counter is updated whenever an idle cell is transmitted. filtered cell counter (fcc) this cell counter is updated whenever an idle/unassigned cell is filtered (discarded). if cell filters are not enabled (tcmode[cf] is cleared), this counter is not updated.
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 52 freescale semiconductor cpm 14.4.21 programming and operating the tc layer the host should first program the mode registers of each tc block to be active, according to the number of tc channels required. then, fcc2 is programmed to work on the utopia interface with the active tc blocks. finally, fcc2 and the phys of the tc channels are enabled . the transmit channels for each tc block are enabled by setting tcmodex[txen]. the receive channels for each tc block are enabled by setting tcmodex[rxen]. the host polls the cd bits of each enabled tc block to verify that its receive cell delineation state machines are synchronized. for every tc block that is synchronized, the host clears the cdt bit in its event register. when all the enabled tc blocks are synchronized, the host terminates its initialization routine, and the system starts normal operation. when a tc block gets out of synchronization, the corresponding tcgsr[cd] is cleared. this change causes a tcer[cdt] interrupt to the host (if enabled). on the receive path, the tc performs the following functions: 1. receives the bit stream via the si. 2. attempts to gain synchronization on the atm cell boundaries by checking each byte (hec candidate) against the hec calculated on the preceding 32 bits (atm cell header candidate). 3. once synchronized, performs the descrambling function on the cell payload (if enabled), performs the coset function on the hec (if enabled), checks for hec errors and corrects single hec errors when found (again, if enabled). cells containing multi-bit header errors (at least 2 errors) are discarded. idle and unassigned cells are filtered (discarded) when detected (if the filters are enabled). once a cell is processed, it passes to the tc receive fifo, and the internal tc cell counters are updated. the cell is passed from the tc receive fifo via the utopia interface to the fcc2 receive fifo. an overrun condition occurs when the tc receive fifo is full, the cp is busy, and the fcc cannot read a cell from it via the utopia interface before another valid cell is received. the incoming cell is discarded and tcer[or] interrupt is sent to the host (if enabled). on the transmit path, once enabled, the tc performs the following functions: 1. starts requesting for cells to send via the utopia interface. 2. when a cell is passed via the utopia interface to the tc transmit block, it is stored in the tc transmit fifo. 3. when a cell is to be sent, it is read from the tc transmit fifo and is processed. the scrambling function is performed on its payload (if enabled), its header hec value is calculated and the coset function is performed on the hec (if enabled). 4. the cell is then sent to the phy via the si. once the cell transmission is complete, the relevant tc cell counters are updated. an underrun condition occurs when a cell is to be sent to maintain the bit rate, but the tc transmit fifo is empty. an idle cell is sent instead. this condition generates a tcer[ur] interrupt (if not masked) if tcmode[ure] is set. when a tc cell counter overflows, an interrupt is set (if enabled). a tc channel provides the data rate dictated by the pmd device by operating the fcc2 in one of two modes: external rate . in this mode, the external device determines the data rate. the cp keeps the fcc fifo full by inserting atm cells or idle cells (if atm cells are not available) into the fcc fifo whenever it is not full. this operation ensures that the cell stream is the data rate required by the pmd. in general, the tc transmit fifo is never empty, and thus would not need to generate idle cells. however, if the cp is busy, and the tc is forced to generate an idle cell because its transmit fifo is empty, an underrun condition occurs. the ur interrupt is sent to the host (if not masked) if tcmode[ure] is set. see figure 23 . this mode generates a greater cp load than the internal rate mode.
cpm functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 53 internal rate (sub rate) . in this mode, the fcc supplies only four phy devices that have four distinct addresses. each channel is controlled by a dedicated hardware timer that is programmed and tuned to the data rate needed. when a timer expires, a valid cell is sent to the corresponding phy. the phy sends idle cells to keep its synchronization and transmission rate. the same is true for the tc. once activated with fcc2 in this mode, the tc requests cells and sends idle cells (ur interrupts can be disabled by clearing tcmode[ure]) until a valid cell is transferred via the utopia bus from the fcc. see figure 24 . operation in byte aligned mode (tcmode[xtba] = 1) is required for t1/e1 mainly. in this mode, once the tc is enabled, it waits for the first txsyn pulse to start transmit the first byte of the first cell. this ensures that subsequent txsyn pulses are byte-aligned to the cell boundaries. figure 23. tc operation in fcc external rate mode figure 24. tc operation in fcc internal rate mode (sub rate mode) fcc phy msc8103 tc dpr cp utopia 2m cell rate 2m serial rate keep fcc fifo full generate idle cells cell_req btm atm channels idle cell at m c e ll (external rate) fcc phy tc dpr cp utopia 1m cell sub rate 2m serial rate 1m sub rate generate cell req brg cell req generate idle cells btm atm channels idle cell at m c e ll (internal/sub rate) write to fifo atm cells only msc8103
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 54 freescale semiconductor cpm 14.4.22 operating the tc layer at higher frequencies the operation of the tc layer requires a minimum frequency ratio of 1:2.5 between the serial clock and the utopia clock (in rx and tx separately). using the tc for serial frequencies greater than 10 mhz requires using higher utopia frequencies to preserve that ratio. 14.4.23 programming a t1 application this section describes how to implement a t1 application using a single tc layer block. using two or more tcs requires fcc2 to work in mphy mode. assuming that the required atm parameters and data structures have been set up and initialized, implementing a t1 application requires the following steps: 1. program fcc2. to set up and initialize fcc2, program the fpsmr and gfmr as shown in ta b le 4 0 . this is for working with one tc block operating in a single phy environment. the transmitter and receiver should not be enabled at this time. in this example, fcc2 does not discard idle cells. 2. set up i/o ports and clocks . because the fcc2 utopia bus is internally connected to the tc utopia bus, program the parallel ports and brgs for the active tdm(s). 3. enable tx/rx on fcc2 . to enable receiving and transmitting, program fcc2 as shown in ta b le 4 1 . 4. program cpm multiplexing . to define the connection of fcc2, program the cpm multiplexing as shown in ta bl e 4 2 . 5. program the tc block . the tcx layer block is configured using the tcmodex and cdsmr1 registers as shown in ta bl e 4 3 . note that the tc layer must be enabled after both fcc2 and the cpm multiplexing are programmed. table 40. programming gfmr and fpsmr to set up fcc2 init values description fpsmr2 = 0x0080_0000 utopia rx and tx in master mode, idle cells are not discarded gfmr2 = 0x0000_000a atm protocol mode, receiver and transmitter are disabled table 41. enable fcc2 init values description gfmr2 = 0x0000_003a enable rx and tx table 42. programming the cpm multiplexing for a ti application init values description cmxfcr = 0x0080_0000 fcc2 is connected to the tc layer cmxuar = 0x0000 fcc2 as utopia master table 43. programming the tc layer block init values description tcmode1 = 0xc202 enable tc layer rx and tx, no error correction on header, the tc is the only phy on utopia cdsmr1 = 0x3980 alpha = 7, delta = 6 (default values)
cpm functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 55 6. program the serial interface (si) . program the si to retrieve the data bits (192 bits) out of the t1 frame (193 bits). the si frame pattern is programmed in the si ram (rx or tx), as shown in table 44 . 7. enable tdm . the initialize the serial interface registers and enable tdm x ?in this case tdma on si1, as shown in ta bl e 4 5 . 14.5 new mcc host commands four new mcc commands are added by the 2k87m mask set as part of the cp command opcodes. table 46 lists the new cp command opcodes changed in the 2k87m mask set. the fields are identical to those defined in the 2k42a mask set, except that definitions have been added for the mcc. ta bl e 4 7 describes the additional commands listed in table 46 ; all other commands are unchanged and are as described in the msc8101 reference manual . table 44. programming the si ram (rx or tx) for a t1 application init values description si_ram[00] = 0x0000 1 bit is ignored. si_ram[02] = 0x015e route 8 bytes to fcc2. si_ram[04] = 0x015e route 8 bytes to fcc2. si_ram[06] = 0x015f route 8 bytes to fcc2 and go back to the first entry in table. table 45. programming si registers to enable tdm init values description si1amr = 0x0040 common receive and transmit pins for tdma si1gmr = 01 enable tdma table 46. 2k87m mask set cp command opcodes opcode channel fcc scc smc (uart/ transparent) smc (gci) spi i 2 c idma mcc timer special 0011 enter hunt mode enter hunt mode enter hunt mode ???? init rx and tx params (one channel) ?? 0101 graceful stop tx graceful stop tx ????? init tx params (one channel) ?? 0110 restart tx restart tx restart tx ???? init rx params (one channel) ?? 0111 close rx bd close rx bd close rx bd ? close rx bd close rx bd ? mcc reset ??
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 56 freescale semiconductor errata 15 errata ta bl e 4 8 lists the functional errata that the 2k87m mask removes and the current 2k87m mask set errata. always refer to the freescale website listed on the back page of this document for a current list of device errata. table 47. 2k87m mask set new command descriptions command description init mcc rx and tx params ? one channel initializes the receive and transmit parameters of the peripheral controller. differs from init rx and tx params in that, for the mccs, issuing init rx and tx params initializes 32 consecutive channels beginning with the channel number specified in cpcr[mcn]. however, issuing init mcc rx and tx?one channel initializes only the channel in the command. init mcc rx params? one channel initializes mcc receive parameters for only a single channel according to mcc channel number field. init tx params? one channel initializes mcc transmit parameters for only a single channel according to mcc channel number field. mcc reset provides a hard reset to the mcc fifos. to use this command, software should execute the following sequence: 1. disable the tdm by clearing the appropriate enable bit in sixgmr[4-7]. 2. issue the mcc reset command. 3. issue the init rx and tx command. 4. reprogram the specific mcc channel, global parameters, and any bds that need to be updated. 5. set the appropriate enable bit in sixgmr[4?7]. table 48. errata resolved in mask set 2k87m errata number errata description applies to mask siu1 wrong timer advancement on rccr date added: 5/30/2000: description: pq2 treats the rccr[timep] value (uc timer) differently then quicc. in quicc the timer advanced (n+1)*1024 cycles and in msc8101 and mpc826x the timer ad- vances n*1024 cycles. workaround: none system number: 1399 0k40a 1k42a 2k42a siu4 incorrect masking of mcp date added: 5/30/2000: description: mcp (machine check interrupt) due to data errors (parity / ecc) is masked by the swri bit in sypcr. workaround: clear the swri bit in sypcr to get data errors indication. system number: 3695 0k40a 1k42a 2k42a
errata functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 57 siu8 parity checking error date added: 6/13/2000: description: during a read from a device with port size less than 64 bits, from an address not aligned to 64 bits, the parity bits for parity check are not taken from the correct locations. for ex- ample, for a read of 4 bytes from a 32-bit port size from address 4, the parity is checked against dp[4?7] while it should be checked against dp[0?3]. the bug exists for both normal and rmw parity, and for both system and local buses. workaround: none system number: 5839 0k40a 1k42a 2k42a siu9 bus monitor asserts spurious tea after address retry. date added: 1/28/2001 description: the bus monitor will not recognize the competition of an address retry transaction and will assert tea if there is no bus activity for a time equal to the expiration time. workaround: disable the bus monitor in systems where address retry cycles are used (e.g. sys- tems which include powerspan). 0k40a 1k42a 2k42a siu10 strict enforcement of requirement to assert dbg and ts in same cycle when core en- abled date added: 1/28/2001 description: this is a compatibility note. an external arbiter must assert dbg in the same clock in which ts is asserted (there may be a one clock delay if the ppc_acr[dbgd] bit is set, how- ever, after reset this bit is not set by default). some external arbiters, including the one implement- ed in powerspan, violate this requirement. as a result, the system hangs following the first bus access after reset. workaround: use only a compliant external arbiter or the internal msc8101 arbiter. 0k40a 1k42a 2k42a qsiu3 tea may hang 60x-compatible bus date added: 5/30/2000 description: tea may hang the 60x-compatible bus if it is asserted between specific address and data phases during a split transaction. workaround: enable bus monitor. fix plan: rev. a 0k40a 1k42a 2k42a qsiu5 incorrect data on 60x-compatible bus date added: 6/13/2000 description: the following sequence on the 60x-compatible bus can result in incorrect data: 1. read transaction with dack before aack . 2. failed atomic write transaction. 3. write transaction. workaround: none. system number: 5823 0k40a 1k42a 2k42a table 48. errata resolved in mask set 2k87m (continued) errata number errata description applies to mask
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 58 freescale semiconductor errata qsiu6 ee[4?5] pins are sampled on hreset ,sreset and poreset date added: 8/31/2000 description: the ee[4?5] pins should be sampled only on poreset , but they are sampled on sreset and hreset as well. changing the value of the ee[4?5] pins after poreset deasser- tion might prevent the chip from booting, because their value might choose a different or unde- fined boot configuration. workaround: the ee[4?5] values should be kept constant and equal to the values on pore- set . 0k40a 1k42a 2k42a qsiu7 pin irq7 _intout not open drain date added: 9/6/2000 description: inout pin irq7_intout should be open-drain but not implemented as one. workaround: buffer intout on the board when it is wire ored. 0k40a 1k42a 2k42a qsiu12 limited clock modes date added: 4/2/2001, modified 2/19/2002 description: single-master and multi-master systems are limited to clock mode 57 for 1k42a and 46 or 57 for 2k42a (see also qsiu14). note that in mode 46 a 33mhz clkin can be used which will result in a 16.5mhz input to the spll. although this is slower than the specified 18mhz (refer to the msc8101 data sheet), this is not an issue in mode 46. 1k42a 2k42a qsiu13 software watchdog cannot be enabled after boot from host date added: 8/5/2001 description: the software watchdog is disabled when booting from host. it cannot be subse- quently enabled because the sypcr can only be written once. workaround: none 0k40a 1k42a 2k42a table 48. errata resolved in mask set 2k87m (continued) errata number errata description applies to mask available 1k42a clock modes modck bus:cpm:core bus:clkin max bus max cpm max core 57 1:2.5:5 1.0 55 138 275 available 2k42a clock modes modck bus:cpm:core bus:clkin max bus max cpm max core 46 1:2:4 2.0 69 138 275 57 1:2.5:5 1.0 55 138 275
errata functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 59 qsiu14 non-functional dll date added: 11/25/2001 description: dll may fail to lock. workaround: use dll disabled mode by setting the dlldis bit in the reset configuration word. to maximize bus performance, use a zero-delay buffer for clkout for both single-mas- ter and multi-master systems. system number: 7427 1k42a 2k42a qsiu15 60x compatible global transaction fail on retry date added: 5/30/2000 description: data may be lost on retry when global transactions are performed in 60x com- patible mode. workaround: when global transactions are used, 60x compatible mode cannot be used. system number: 5678 0k40a 1k42a 2k42a qsiu16 ale output during reset date added: 2/20/2003 description: ale behavior is not guaranteed during reset. this affects only multi-master sys- tems which perform reset configuration from external memory and which use ale for all memory accesses. ale recovers with the first access after reset. workaround: none system number: fix plan: reva 0k40a 1k42a 2k42a dma1 dma data corruption on either ppc bus or local bus date added: 2/19/2002 description: data transferred by the dma on either the ppc bus or local bus may be corrupted. workaround: for dma accesses on the ppc bus - disable ppc bus pipeline by setting bcr[pldp]=1. for dma accesses on the local bus the upmc programming patch is available. system number: 7462 0k40a 1k42a 2k42a boot1 incorrect checksum for host bootload date added: 8/15/2000: description: the host bootload calculates erroneous checksum. workaround: clear icr[hf3] so that the host bootload ignores the checksum comparison result. system number: 6178 0k40a 1k42a 2k42a table 48. errata resolved in mask set 2k87m (continued) errata number errata description applies to mask
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 60 freescale semiconductor errata boot2 boot interference in multi-master system with shared memory date added: 8/5/2001 description: the dspram address in the memory map as programmed by the boot loader code in the rom is the same for all processors. during simultaneous boot, this will cause interference of one processor with another. workaround: for up to 4 msc8101?s including the configuration master. boot the processors one after the other, and not at the same time. reprogram unique dspram address for each processor. the configuration master is set also to be the arbitration master and the memory controller for the system. the configuration word for the master should set the mmr field of the reset word (bits [18:19]) to 2'b11. this will mask all the external bus requests of the configuration slaves. after the master completes its boot, the user should: 1. clear all external requestors from the arbitration level register (alr) of the arbi- tration master. 2. reprogram the upm of the dspram bank to unique address (see programming example below) 3. set priority for the next configuration slave in the arbitration level register (alr) of the arbitration master. 4. enable external bus requests by clearing siumcr mmr field (bits [16:17]). 5. repeat stages 2,3 for consecutive slaves. configuration master programming code: move.l ppc_alrh,d7 ; step #1 move.l ppc_alrl,d8 bmclr.w #$f,d7.l bmclr.w #$ff00,d8.h move.l d7,ppc_alrh move.l d8,ppc_alrl upmc_init $04000000 ; step #2 (dspram base address $0400_0000) move.l ppc_alrh,d7 ; step #3 nop bmset.w #$7,d7.l nop move.l d7,ppc_alrh move.l siumcr,d7; step #4 nop bmclr.w #$c000,d7.l nop move.l d7,siumcr 0k40a 1k42a 2k42a gen1 device withstands mm esd of 75v instead of 100v date added: 5/21/2002 description: device meets the esd specifications for human body model (hbm) of 1000v and charged device model (cdm) of 500v but does not withstand the machine model (mm) re- quirement of 100v. all pins guaranteed to withstand 75v mm. workaround: none. 0k40a 1k42a 2k42a table 48. errata resolved in mask set 2k87m (continued) errata number errata description applies to mask
errata functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 61 gen2 unexpected outputs during boundary scan date added: 10/18/2002 description: d[32:60] outputs may behave indeterminately during boundary scan. workaround: reset the device by asserting poreset while hpe/ee1=0. alternatively, assert poreset throughout boundary scan. fix plan: reva 0k40a 1k42a 2k42a sc1 pc cannot be updated in debug mode entered from asynchronous interrupt date added: 10/5/2000 description: when a debug instruction is executed in a static or dynamic delay slot created by an asynchronous interrupt, the core enters debug mode, but the pc cannot be updated. workaround: in the dynamic case, the debugger can use a status bit in the esr, which indicates whether the core entered a debug in a delay slot. software workarounds are available for all the static cases. a detailed description was sent by starcore and can be resent upon request. 0k40a 1k42a 2k42a sc3 erroneous trace buffer value date added: 10/5/2000 description: an erroneous 62-bit value may be written to the trace buffer when the eonce is programmed to write both event counters (ecnt_val and ecnt_ext). workaround: none. 0k40a 1k42a 2k42a cpm2 cam access not atomic date added: 5/30/2000: description: the bus atomicity mechanism for cam access may not function correctly when the cpm?s dma accesses the cam. this only affects systems in which multiple cpms will ac- cess the cam. workaround: none system number: 1410 0k40a 1k42a 2k42a cpm4 no cts lost indication with hdlc date added: 5/30/2000 description: when cts is deasserted at the end of hdlc frame, (last flag or one bit before) trans- mission will be aborted. however there is no cts-lost indication. there is only abort indica- tion. workaround: none system number: 1670 0k40a 1k42a 2k42a cpm5 data corruption on sdma flyby date added: 5/30/2000 description: the data of a sdma write, which follows a sdma flyby read in the local bus may be corrupted. workaround: none system number: 1720 0k40a 1k42a 2k42a table 48. errata resolved in mask set 2k87m (continued) errata number errata description applies to mask
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 62 freescale semiconductor errata cpm6 erroneous report of overrun on fcc date added: 5/30/2000 description: spurious overrun indications on the fcc may occur in the following cases: 1. after stop transmit command is issued. 2. following cts lost condition. 3. late collision under ethernet. workaround: none system number: 1746 0k40a 1k42a 2k42a cpm7 erroneous report of overrun with fast ethernet date added: 5/30/2000 description: if the crs (carrier sense) signal is deasserted while fast ethernet frame is transmit- ted, an overrun error may occur and the fcc may have to be reset. workaround: none system number: 1752 0k40a 1k42a 2k42a cpm8 error on transmit on demand register date added: 5/30/2000 description: the todr mechanism may freeze serial channels. workaround: do not use todr. system number: 2484 0k40a 1k42a 2k42a cpm9 erroneous reception of atm cell date added: 5/30/2000 description: under certain conditions, an atm receiver may receive cells of phys which were not addressed for it. details of the condition: atm receiver in utopia slave mode. fifo full condition occurred (this happens only when the transmitter violates the utopia standard requirements: transmits data without clav). transmitter changed selected phy number. fifo full condition ended (cpm read some data from fifo). workaround: use different vpi/vci for different phys or expect the cells to be discarded by higher-level protocol software. system number: 2493 0k40a 1k42a 2k42a cpm10 error in atm underrun report date added: 5/30/2000 description: in atm, a transmit internal rate underrun error is not reported correctly in the tiru field of the fcce register. in most cases, tiru is not set in the fcce when an internal rate underrun error occurs. in some rare cases that depend on internal sequences within the communi- cations controller, the tiru bit may be set as expected when the error should be reported. workaround: none system number: 2611 0k40a 1k42a 2k42a table 48. errata resolved in mask set 2k87m (continued) errata number errata description applies to mask
errata functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 63 cpm11 false indication of shared flag date added: 5/30/2000 description: fcc-tx hdlc - fct_txd (data out) changes from 1-->0 for 1 ser_clock period, few clocks after the reset command from main is given. a false shared flag can be detected at the receiver if the last bit before reset was 0, and the receiver considers it as a closing flag of the frame. in most of cases, a crc error is generated and the frame is discarded. workaround: none system number: 3024 0k40a 1k42a 2k42a cpm13 error in random number generation date added: 5/30/2000 description: in fast ethernet transmit, when more then one (up to four) frames reside in the fcc fifo, random number generation (for collision wait) may produce the same number for all four frames. workaround: none system number: 3421 0k40a 1k42a 2k42a cpm14 corruption of atm cells date added: 5/30/2000 description: corruption of atm cells may occur when the following combination is used: aal1 with udc in which the user-defined header size is 9 to 12 octets and pm is not used. workaround: since this problem appears in a very specific condition as described above, avoid- ing any of the elements (e.g., using cell header of 8 octets) eliminates it. 0k40a 1k42a 2k42a cpm15 corruption of port d registers date added: 5/30/2000 description: the pdata, pdatb, pdatc, and pdatd registers can only be written with a 32-bit write instruction. (i.e., stw). when 8- or 16-bit write instructions (i.e., sth, stb) are used, the bits not being written may be corrupted. workaround: use a 32-bit write instruction only to write to the pdata, pdatb, pdatc, and pdatd registers. system number: 3679 0k40a 1k42a 2k42a cpm17 error in reporting utopia error condition date added: 5/30/2000 description: an fcc receiver which is configured as single phy master does not detect a uto- pia error condition when soc and clav are not asserted simultaneously. system number: 3728 0k40a 1k42a 2k42a cpm21 false indication of collision in fast ethernet date added: 5/30/2000 description: in the fast ethernet a false col is reported whenever a collision occurs on the pre- amble of the previous frame. workaround: s/w should ignore col indications when the crc of the frame is correct. system number: 3927 0k40a 1k42a 2k42a table 48. errata resolved in mask set 2k87m (continued) errata number errata description applies to mask
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 64 freescale semiconductor errata cpm22 false defer indication in fast ethernet date added: 5/30/2000 description: in the fast ethernet, if a frame is transmitted due to defer and this frame also gets late collision, a false defer indication is indicated for the next frame. workaround: none system number: 3981 0k40a 1k42a 2k42a cpm24 error in indicating idle between frame date added: 5/30/2000 description: in the fcc hdlc transmitter, if slow serial clock (cpm_freq/serial_clock > 16) is used, rts does not transition to idle between frames. this means that all the frames are trans- mitted back-to-back in case there is valid data in the transmitter?s fifo. workaround: none system number: 3998 0k40a 1k42a 2k42a cpm27 error in heartbeat checking in fcc date added: 5/30/2000 description: the heartbeat checking in fcc transmit ethernet 10mbps does not work properly. the standard requires that the collision pulse from the phy should be checked within a window of 4 sec from the falling edge of the carrier sense. the pq2 samples the collision signal only once at exactly 4 sec (10 serial clocks) after the falling edge of the carrier sense signal. workaround: none system number: 4155 0k40a 1k42a 2k42a cpm28 error in receive frame threshold date added: 5/30/2000 description: in the scc rx in hdlc mode, rfthr does not work. there is no way to get in- terrupts on the receive side after a programmable number of frames. workaround: rfthr should be programed to 1. system number: 4163 0k40a 1k42a 2k42a cpm29 maxd1 and maxd2 may not be less than mflr date added: 5/30/2000 description: in scc rx ethernet, the option of transferring only part of a frame into memory (maxd1 and maxd2 < mflr) does not work. workaround: none system number: 4166 0k40a 1k42a 2k42a cpm30 graceful stop command does not work date added: 5/30/2000 description: the graceful stop command does not work in scc tx in the following protocols: ethernet, hdlc, transparent. workaround: none system number: 4167 0k40a 1k42a 2k42a table 48. errata resolved in mask set 2k87m (continued) errata number errata description applies to mask
errata functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 65 cpm35 data corruption in scc transparent mode date added: 5/30/2000 description: when scc transparent, envelope mode is used and the received frame size is (4*n) + 1, the last byte is corrupted. when gsmr_h(rfw) - rx fifo width is used, the received data is completely corrupted, not just the last byte. workaround: the bug can be worked around with a microcode patch. system number: system number; 4350 0k40a 1k42a 2k42a cpm36 si sync timing restriction date added: 5/30/2000 description: si?s sync signal may not change exactly on clock edge in the following cases. the bug affects operation only when the si is in one of two modes: fsd = 00, ce = 0, fe = 0, dsc=1 (sync sampled with falling edge -> sync should not change on rising edge) fsd = 00, ce = 1, fe = 1, dsc=1 (sync sampled with rising edge -> sync should not change on falling edge). workaround: when working in these modes, the sync signal to the si should be manipulated such that it does not change on the exact edge of the serial clock. toggle the sync at least 5ns after the edge. one way to implement such a workaround is to add a noninverting buffer between the device that generates the sync signal and the msc8101 that uses it. system number: 3258 0k40a 1k42a 2k42a cpm38 heartbeat error and carrier sense lost error on two frames date added: 5/30/2000 description: there are rare cases when a heartbeat error and carrier sense lost error are reported on two frames. the error is reported in the frame in which it occurred, but in those rare cases it is also reported on an adjacent frame. workaround: none system number: 1547,1550 0k40a 1k42a 2k42a cpm39 corruption in aal0 cell payload date added: 5/30/2000 description: there is a rare case in using the atm aal0 transmitter that the aal0 cell payload may be corrupted. this can occur in certain internal sequence of events that the user cannot detect or control. workaround: 1. use the available microcode patch from the web site. 2. when working with aal0 sar, place the tcell_tmp_base 64 byte align plus 4. for example use tcell_tmb_base = 0x2d04 not 0x2d00. system number: 4648a 0k40a 1k42a 2k42a table 48. errata resolved in mask set 2k87m (continued) errata number errata description applies to mask
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 66 freescale semiconductor errata cpm40 corruption in aal0 idle cell date added: 5/30/2000 description: there is a rare case when transmitting an atm idle cell that the idle cell may be corrupted. this can occur in certain internal sequences of events that cannot be controlled or de- tected by the user. workaround: place the idle base template at address 64 byte align minus 4. for example use idle_base = 0x2cfc not 0x2d00. system number: 4648b 0k40a 1k42a 2k42a cpm41 limitation in atm controller date added: 5/30/2000 description: there are some limitations in the atm controller. the first limitation is that only the first 8 pm tables can be used instead of 64. when using these 8 tables, the user must clear the 5 most significant bits of tbd_base (in case of tx pm) or rbd_base (in case of rx pm). the second limitation is that only the first 2048 atm channel numbers can be used. workaround: there is a microcode patch that can fix the pm limitation. the atm channel number limitation has no workaround. system number: 4744 0k40a 1k42a 2k42a cpm42 data corruption in mcc date added: 5/30/2000 description: data corruption may occur in the receive buffers of mcc channels when more then one tdm slot uses 7 bits of contiguous data. workaround: it is possible to avoid this problem by splitting the 7 bits slots between two si ram entries such that one entry will represent 4 bits of the slot and the other si entry will represent 3 bits of the slot. the errata occurs only when all the 7 bits are represented by one entry in the si ram. system number: 4743 0k40a 1k42a 2k42a cpm43 txclav ignored by utopia in single phy mode date added: 5/30/2000 description: when the fcc transmitter is configured to work in utopia single phy master mode, it ignores deassertion of the txclav signal. therefore, the utopia slave cannot control the flow of cells by deasserting txclav . note that this bug affects rev a.1 chips only. workaround: configure the fcc to work in multi-master mode but limit the number of phys to 1 by programming: fpsmr[last phy] = 5?b0 system number: 4882 0k40a 1k42a 2k42a cpm44 zero insertion error on mcc date added: 5/30/2000 description: when the mcc transmitter is used in hdlc super channel mode, a zero insertion at the last bit before the flag fails to occur. workaround: there is a microcode patch which fixes the problem. system number: 4941 0k40a 1k42a 2k42a table 48. errata resolved in mask set 2k87m (continued) errata number errata description applies to mask
errata functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 67 cpm45 error in clav sample point date added: 5/30/2000 description: in fcc atm transmit master mode (multiple phy only), the clav signal is sam- pled 5 clocks before the end of the cell instead of 4 clocks. this is relevant only for back-to-back transmission sequence. workaround: in multiple phy fix priority polling mode, by adding a dummy phy, it is possible to ensure that the dummy phy is polled at payload 44 (5 clocks before the end of the cell). this is possible since the cell length is constant and the number of phy to poll is also constant. system number: 5031 0k40a 1k42a 2k42a cpm46 error in internal prioritization of cpm resource date added: 5/30/2000 description: each of the communication controllers (fcc, mcc, scc, ...) issues request for service to the cpm with different priorities in order to receive the necessary assistance in time. because of an internal connection error, the fcc3 request for service is issued with a much lower priority than intended. because of this, fcc3 may sporadically overrun when the cpm is heavily loaded. workaround: none system number: 5663 0k40a 1k42a 2k42a cpm48 error in tdm date added: 5/30/2000 description: disabling tdmx may interfere with the operation of tdmy if tdmy uses the si- ram blocks directly above those used by tdmx. for example: start address of tdmc = 0 start address of tdmb = 2 start address of tdma = 4 start address of tdmd = 6 when disabling tdma, tdmb is affected. when disabling tdmb, tdmc is affected. when disabling tdmd, tdma is affected. when disabling tdmc, no tdm is affected. workaround: instead of disabling a tdm, the user can switch to a shadow ram that contains only non supported slots in its entries. system number: 5714 0k40a 1k42a 2k42a cpm49 error in fec cam address recognition date added: 3/14/2002 description: external cam address recognition in fast ethernet controller does not function. workaround: use microcode patch available from freescale. system number: 5404 0k40a 1k42a 2k42a table 48. errata resolved in mask set 2k87m (continued) errata number errata description applies to mask
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 68 freescale semiconductor errata cpm50 mcc transparent super channel loss of alignment date added: 5/30/2000 description: when the mcc is configured to work in transparent, super channel first sync slot synchronization, loss of alignment may occur when the first data (idles) on the rx data line match- es the value of the rcvsync parameter. workaround: write to rcvsync a pattern which cannot appear in the rx data line. system number: 5833 0k40a 1k42a 2k42a cpm54 error in switching to and from shadow si ram. date added: 12/10/2000, modified 15/0/2002 description: dynamic switching in siram may not be executed properly. workaround: in si ram, when working with shadow ram, the last entry (n) and the entry im- mediately before the last entry (n-1) must have at least one common bit in the cnt or byt fields. for example: siram entry cnt byt n-1 000 1 n 010 1 the above is okay n-1 101 0 n 001 0 the above is okay n-1 100 0 n 001 0 the above is not okay. system number: 6282, 6283 0k40a 1k42a 2k42a cpm55 error in atm_transmit command. date added: 12/10/2000 description: the atm_transmit command does not execute correctly when used on apc pri- ority above 4. workaround: none. system number: 6162 0k40a 1k42a 2k42a cpm57 aal5 cell corruption. date added: 1/28/2001 description: the second part of a second cell may overwrite the second part of the first cell in an aal5 frame. workaround: use microcode patch. 0k40a 1k42a 2k42a table 48. errata resolved in mask set 2k87m (continued) errata number errata description applies to mask
errata functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 69 cpm64 aal5 rxbd[lne] error generated if pdu length exceeds 65512 bytes date added: 5/31/2001 description: when the cpm receives an aal5 pdu between 65512-65535 bytes (maximum length) the cpm sets the rxbd[lne] indicating a receive length error, however the memory buffer contents for the pdu are correct. workaround: receive aal5 pdu less than 65512 bytes or use microcode patch. system number: 7025 0k40a 1k42a 2k42a cpm65 ss7 microcode in rom does not function correctly date added: 8/5/2001 description: the ss7 microcode in rom does not function correctly and should not be used. workaround: use the enhanced ss7 microcode package. 0k40a 1k42a 2k42a cpm71 cpm does not snoop mcc buffer descriptors. date added: 8/5/2001 description: when the mcc performs a dma read or write of the buffer descriptor, gbl is not asserted and tc2 is always driven low.therefore cache snooping will not be enabled for mcc bds, therefore bds in memory will not match the data cache. also the bus used for the dma is always the 60x, therefore if the bds are on the local bus then the dma consumes bandwidth on both the 60x and local bus. workaround: if gbl and/or tc2 are set in the mcc tstate/rstate parameters, use mi- crocode patch available from freescale which fixes the above problem. if gbl and tc2 are not set to improve performance move the mcc bds to the 60x bus. the microcode patch will fix both the gbl/tc2 and the bus performance issue. system number: 7018 0k40a 1k42a 2k42a cpm72 mcc global underruns date added: 8/5/2001 description: an mcc transmitter global underrun (gun) error may result from intensive activ- ity on fcc1 (e.g.burst of short back to back ethernet frames).this is due to the prioritization of the mcc transmitter relative to fcc1 receiver and transmitter as well as the mcc receiver. workaround: each serial channel above can request a service at normal or emergency level. in case of emergency, the request is handled before normal (non-emergency) request of the channels at a higher priority level.the proposed change is to allow the mcc transmitter to assert an emer- gency request instead of normal request. the impact on fcc1 in this case is minimal.this feature will controlled by a new mcc mode bit in future msc8101 revisions. this new mcc mode bit will allow users to continue to use the current cpm priority scheme in their applications if re- quired. 0k40a 1k42a 2k42a cpm73 si ram corruption date added: 8/5/2001 description: (7049)an access to the si ram bank from the 60x bus while the corresponding tdm is active may result in data corruption within the si ram. workaround: associate the si ram bank with an inactive tdm before attempting to access it. once the accesses has been made, the si ram bank should be re-assigned to the active tdm. system number: 7049 0k40a 1k42a 2k42a table 48. errata resolved in mask set 2k87m (continued) errata number errata description applies to mask
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 70 freescale semiconductor errata cpm74 fcc hdlc controller stops transmitting when using nibble mode with mff=0 date added: 8/27/2001 description: when running an fcc in hdlc nibble mode with the multi-frame per fifo bit off (mff=0) the cpm may lose synchronization with the fcc hdlc controller. as a result the hdlc controller will get stuck and stop transmission. workaround: when running the fcc in hdlc nibble mode set the mff=1 or alternatively run the fcc in hdlc bit mode. 0k40a 1k42a 2k42a cpm76 first transmitted bit zero in fcc transparent mode with gfmr[ctss]=1 date added: 8/27/2001 description: when using an fcc in transparent mode the first bit of a frame is transmitted as zero every time rts is asserted before cts is asserted when cts is sampled synchronously with data (gfmr[ctss]=1). if cts is in pulse mode (gfmr[ctsp]=1) only the first frame is affect- ed because cts is ignored thereafter. if cts is not in pulse mode (gfmr[ctsp]=0) then every frame is affected separately. workaround: if the receiver synchronizes on a 8/16-bit sync pattern stored in the fdsr register (gfmr[synl]=1x) ensure that the synchronization pattern starts with a ?0?. if no synchroniza- tion pattern is used (grmr[synl]=0x) add a one-byte dummy buffer before sending the real data buffers. 0k40a 1k42a 2k42a cpm79 fcc fast ethernet flow control date added: 3/14/2002 description: when the fcc receives a flow control pause message with mac parameter =0xffff, it sets a zero delay instead of maximum delay. 0k40a 1k42a 2k42a cpm80 mcc ces user template date added: 3/14/2002 description: if the transparent mcc tx ces channel requires the user template (chamr[utm]=1) only the first 8 bytes of the user defined pattern are transmitted. then the transmitter will continue to send bytes 4-7 of the pattern continuously until the counter reaches 0. any bytes defined in the pattern after byte 7 are never transmitted. workaround: use a template size of 8 bytes. 0k40a 1k42a 2k42a cpm85 only one bsy interrupt generated for aal0 date added: 5/21/2002 description: when using aal0, only one bsy interrupt will be received regardless of the num- ber of bsy events that are generated. workaround: none. 0k40a 1k42a 2k42a table 48. errata resolved in mask set 2k87m (continued) errata number errata description applies to mask
errata functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 71 cpm86 random phy number for fcc rx in single-phy master mode date added: 5/21/2002 description: when the fcc receive atm controller is configured for single phy master mode (fpsmr[rump]=0, fpsmr[rums]=0) and fpsmr [last phy / phy id] is not equal to ze- ro, a random phy id might be allocated to the incoming cells instead of the expected zero (for single-phy). this will result in a loss of cells. this configuration is typical when using the fcc transmit atm controller in multi-phy master mode together with the fcc receive atm con- troller in single phy master mode. workaround: the address lookup mechanism should be created in such a way that for any phy addr input, the output will be as for phy 0. 0k40a 1k42a 2k42a cpm88 mcc transmit gun when mcc stop rx cpcr command is used date added: 10/15/2002 description: an mcc may experience a highly intermittent transmit gun event indication, re- lated to mcc receive channels that have been stopped via the mcc stop rx host cpcr com- mand. this gun can happen unrelated to internal cpm loading or other external factors. workaround: avoid using mcc stop rx command using one of the following mechanisms: 1. simply stop the tdm or 2. use shadow ram and dynamically remove the desired mcc rx channel entry from siram programming (see 8260 user manual chapter 14). the following pro- cedure should be utilized, using an extra redundant shadow ram switch. this is done to provide a full tdm frame?s amount of time to ensure receive activity is complete and will avoid the issue: a. re-program shadow siram to remove channel to be stopped. b. switch to shadow siram and wait for that tdm?s bit in the sixstr register to change to indicate switch complete. c. copy this new shadow ram programming back to the main siram bank. d. switch to active ram, again wait for switch to complete. e. then software can re-initialize or modify the removed channel?s rx parameters. system number: 2905 fix plan: reva 0k40a 1k42a 2k42a cpm95 atm false indication of mis-inserted cells date added: 2/25/2003 description: there is a false indication of unassigned bits in the phy:vpi:vci which could cause atm cells to be treated as mis-inserted cells and therefore be discarded. workaround: use microcode patch available from freescale. fix plan: reva 0k40a 1k42a 2k42a table 48. errata resolved in mask set 2k87m (continued) errata number errata description applies to mask
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 72 freescale semiconductor errata cpm100 abr tcte address miscalculation description: when using the aal5 abr rom microcode with external atm channels it is pos- sible for the ext_tcte_base word value (written by the user to dpram) to be misread. in this case calculations performed by the microcode to access the users programmed external tcte will be incorrect with a high chance of the access resulting in a cpm crash. workaround: use the micro code patch available from freescale. system number: 9131 fix plan: rev. a 0k42a 1k42a 2k42a cpm110 fcc1 prioritization date added: 12/19/2003 description: the fcc1 receiver in ethernet, hdlc, or transparent controller mode is not ele- vated to emergency status (priority 4 in table 19-2 of the reference manual, "peripheral prioriti- zation"), which may lead to a fifo overrun if the system is heavily loaded (fcc1 receiver has the highest priority excluding emergency status of other peripherals) . workaround: when allocating fccs, assign fcc2 and fcc3 for ethernet, hdlc or transpar- ent before fcc1, or assign fcc1 to the lowest bit rate interface. if fcc1 is allocated for atm and requires higher cpm usage than the other fccs, disable its emergency status. system number: 11062 fix plan: 0k40a 1k42a 2k42a table 49. errata resolved by specification change in mask set 2k87m errata number errata description applies to mask qsiu8 core tea not supported as nmi date added: 9/7/2000 description: q2ppc tea is not supported on pic nmi5. workaround: use pic irq19 . resolution: specification is changed to reflect this state in mask set 2k87m. 0k40a 1k42a 2k42a 2k87m siu15 data not written to the sdram in rmw parity mode date added: 5/21/2002 description: when using a read-modify-write parity mode and pipelined addresses on the sdram interface, the write portion of the rmw might be performed as a read. as a result, the data is not written to the external memory. workaround: use bcr[pldp]=1 for a pipeline depth of zero. fix plan: none, specification is changed so that this is defined as normal functionality and be- comes a documentation errata. 2k87m table 48. errata resolved in mask set 2k87m (continued) errata number errata description applies to mask
errata functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 73 cpm37 requirement for software to disable fcc after error date added: 5/30/2000 description: there are four errors in the fcc transmitter that require software to disable and en- able the transmitter before it can continue to operate correctly. the four errors are: 1. cts-lost indication in the hdlc transmitter 2. late collision in the fast ethernet transmitter 3. underrun in any of the fcc transmitter protocols 4. expiration of rl in fast ethernet workaround: none available. system number: 4040, 3980, 2314 fix plan: specification was changed to include details for error handling software. 0k40a 1k42a 2k42a 2k87m table 50. 2k87m errata errata number errata description applies to mask siu13 sdamux not valid in single-msc8103 mode date added: 3/14/2002 description: sdamux signal is disabled (stuck at ?0?) when sdram machine handles the memory access and the chip is programmed to single-msc8103 mode (bcr[ebm]=0). workaround: none. 0k40a 1k42a 2k42a 2k87m siu16 bus busy disable mode can hang 60x bus in multi-master systems date added: 5/21/2002 description: the bus busy disable mode (siumcr[bbd=1]) can not be used if the msc8103 is not the only master on the 60x-compatible bus. using this mode in such a system can cause the 60x-compatible bus to hang. workaround: 1. if the external master supports the abb signal, do not use the bus busy disable mode and connect this signal to the msc8103. the dbb signal can either be connected or can be pulled up. 2. if the external master does not support the abb signal do one of the following: a. do not use the bus busy disable mode and generate the abb signal externally. the dbb signal can either be connected or can be pulled up. the following external abb implementation should be sufficient to work around the problem: assert the abb signal whenever a qualified bus grant for the external master is sampled (bus grant asserted while artry and abb are deasserted). deassert the abb signal when there is no qualified bus grant. the deassertion of abb should be as follows: drive abb to v dd for half a clock cycle and then stop driving it (high impedance). b. if using the internal arbiter and up to two external masters, connect the external bus grants (through an and gate if more than one) to an available external bus request and define the priority for that request to be the highest in the ppc_alrh register. the dbb signal can either be connected or can be pulled up. fix plan: tbd 2k87m table 49. errata resolved by specification change in mask set 2k87m (continued) errata number errata description applies to mask
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 74 freescale semiconductor errata siu18 artry assertion when using pipeline depth of zero date added: 10/15/2002 description: internal (60x) slave maintains a pipeline depth of zero by asserting aack only af- ter ta. when artry is asserted the 60x bus access will be terminated and ta will not be as- serted. therefore the internal (60x) slave will not assert aack since ta was not asserted. workaround: use a pipeline depth of one (bcr[pldp]=0) for applications that require mem- ory coherency. fix plan: tbd 0k40a 1k42a 2k42a 2k87m siu19 bus monitor timeout when using external slave date added: 10/15/2002 description: when using an external 60x bus slave with the bus monitor activated, psdval is not asserted when the external slave is accessed, which could cause the bus monitor to time-out and tea to be asserted. workaround: the following workarounds 1. use pipeline depth of zero (bcr[pldp]=1) when using an external 60x bus slave. 2. disable 60x bus monitor, sypcr[pbme]=0. 3. if the external 60x bus slave is another 810x or 826x device, connect the psdval signals together. fix plan: tdb 0k40a 1k42a 2k42a 2k87m qsiu4 extended mode on local bus date added: 6/13/2000 description: using extended mode on the local bus can generate incorrect transactions in certain combinations of consecutive reads and writes. workaround: do not use extended mode on the local bus. system number: 5959 fix plan: tbd 0k40a 1k42a 2k42a 2k87m efc1 inaccurate efcop iir outputs for two or fewer coefficients date added: 8/15/2000 description: when using normal (dual) dma or flyby dma transfers which have a maximum transfer size greater than 32 bits with the efcop to perform iir filtering with two or less iir co- efficients, the first output of the iir filter is lost. the rest of the outputs are shifted and inaccurate. workaround: use only dma 32-bit maximum transfer size for both input and output channels. fix plan: tbd 0k40a 1k42a 2k42a 2k87m gen3 device withstands esd cdm stress of 400 v instead of 500 v date added: 10/31/2002 description: device meets the esd specifications for human body model (hbm) of 1000 v and machine model (mm) of 100 v but does not withstand the charged device model (cdm) of 500 v. all pins are guaranteed to withstand cdm of 400 v. workaround: na fix plan: tbd 2k87m table 50. 2k87m errata errata number errata description applies to mask
errata functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 75 sc4 sc140 core may hang after write to the pctl0 register date added: 2/19/2002 description: write to the pctl0 freezes the core immediately for 150?190 cycles. if the system is busy (for example, doing pre-fetch transactions), the core may not exit the freeze state. workaround: option a: 1. ensure the efcop is not active. 2. ensure the local bus to l1 memory is not active. 3. ensure that the program that writes to pctl0 is in internal memory. 4. write to pctl0 immediately after reset before any external accesses. option b: do not write to pctl0. system number: 7560 fix plan: tbd 0k40a 1k42a 2k42a 2k87m sc5 sc140 core may hang after illegal execution set date added: 2/19/2002 description: upon receipt of an illegal execution set, the sc140 core may enter a freeze state that can only be released by reset. workaround: none available. system number: 7541 fix plan: tbd 0k40a 1k42a 2k42a 2k87m sc6 incorrect data on trace buffer during core freeze date added: 2/19/2002 description: after writing data to the trace buffer (tb), the tb is disabled in order to read from it. there are two options to read the tb and the problem occurs in both: 1. reading the tb by software. if a core freeze occurs while the software reads the tb into a core register, data can overwrite the previous data. 2. reading the tb from jtag. if a core freeze occurs while the jtag is reading the tb, the data is not correctly sampled. workaround: 1. software: read the tb by software when there is no core freeze: a. ensure that the program is in internal memory. b. ensure that the efcop is not active. c. ensure that the local bus to l1 memory is not active. d. ensure that the write buffer is empty. e. ensure that there are no other move commands except for the tb read. 2. jtag: a. read the tb from jtag only when the core is in debug mode. b. before reading the tb, flush the write buffer. system number: 7604 fix plan: tbd 0k40a 1k42a 2k42a 2k87m table 50. 2k87m errata errata number errata description applies to mask
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 76 freescale semiconductor errata sc7 change of flow may cause incorrect trace-buffer data date added: 2/19/2002 description: when the eonce module is programmed for tracing events of change of flow (tchof) and interrupts (tint), the trace buffer is updated on every event by the source and destination addresses. in the event of a change of flow (chof) to another chof with an interrupt request in between, the trace buffer is updated with additional data. the additional data is incor- rect and is not needed for the trace. workaround: perform post-processing after reading the trace buffer. search in the data for a source address with its destination listed before it. delete the source and the previous data. system number: 7794 fix plan: tbd 0k40a 1k42a 2k42a 2k87m sc8 debug exception request from jtag is not accepted during core freeze date added: 5/21/2002 description: jtag debug exception request is not accepted by the core during freeze. if the re- quest is asserted and deasserted during a core freeze, the request is discarded. workaround: assert debug request from jtag. when entering the exception routine, use soft- ware to assert an external pin (one of the ee pins, for example) to signal that the exception ser- vice routine was executed. after that, a new jtag instruction can be written. fix plan: tbd 0k40a 1k42a 2k42a 2k87m sc9 ee pins do not enable different eonce modules during core freeze date added: 5/21/2002 description: if ee pins are asserted to enable events in the eonce modules during a core freeze and the request is deasserted during the same core freeze, the event is not enabled. workaround: poll core status from jtag. after the core is not in a freeze state, assert the ee pin(s) for at least three cycles. fix plan: tbd 0k40a 1k42a 2k42a 2k87m cpm94 fcc rts signal not asserted correctly date added: 2/25/2003 description: at the beginning of an hdlc frame transmission which is preceded by more than one opening flag, rts will not be asserted if cts is negated. this may cause a deadlock if the modem waits for the assertion of rts before asserting cts . workaround: implement one of the following: 1. transmit no flags between or before frames. 2. clear fpsmr[nof] bit. set gfmr[rtsm]=1 to ensure rts/ is asserted when fcc is enabled. however no hand shaking activities with the modem will occur for all the proceeding frames. fix plan: tbd 2k87m cpm96 atm performance monitoring with aal1 ces date added: 2/25/2003 description: atm performance monitoring with aal1 ces data in dpram is corrupted when performance monitoring is enabled in the receiver. workaround: impelement one of the following: 1. disable receive performance monitoring rct[pmt]=0. 2. use microcode patch available from freescale. fix plan: tbd 0k40a 1k42a 2k42a 2k87m table 50. 2k87m errata errata number errata description applies to mask
errata functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 77 cpm97 mcc ss7 - no suerm interrupt generated after an abort date added: 2/25/2003 description: octet count mode is not entered properly when idles are received after an abort. therefore n_cnt is not decremented and no suerm interrupt will be generated. this problem only affects the ss7 micro code in itu-t / ansi mode (ss7_opt[std]=0). workaround: use the latest ram based ss7 micro code package available from freescale. fix plan: tbd 2k87m cpm98 i 2 c erratic behavior can occur if extra clock pulse is detected on scl date added: 8/25/2003 description: the i 2 c controller has an internal counter that counts the number of bits sent. this counter is reset when the i 2 c controller detects a start condition. when an extra scl clock pulse is inserted in between transactions (before start and after stop conditions), the internal counter may not get reset correctly. this could generate partial frames (less than 8 bits) in the next transaction. workaround: do not generate extra scl pulses on the i 2 c bus. in a noisy environment the dig- ital filter i2mod[flt] and additional filtering capacitors should be used on scl to eliminate clock spikes that may be misinterpreted as clock pulses. system number: 9133 fix plan: tbd 0k42a 1k42a 2k42a 2k87m cpm99 abr tcte[er-ta] corruption date added: 8/25/2003 description: when using the aal5 abr rom microcode it is possible for the tcte[er-ta] field to be overwritten with an erroneous value. this, in turn, will cause the tcte[er-brm] to be updated with this value. as tcte[er-brm] holds the maximum explicit rate value allowed for b-rm cells an erroneous value in this field could have a detrimental effect on the network performance. workaround: use the micro code patch available from freescale. system number: 9132 fix plan: tbd 0k42a 1k42a 2k42a 2k87m table 50. 2k87m errata errata number errata description applies to mask
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 78 freescale semiconductor errata cpm101 fcc rxclav timing violation (slave) date added: 1/15/2004 date revised: 11/05/2004 description: fcc atm receive utopia slave mode. when the rxfifo is full, rxclav is ne- gated 2 cycles before the end of the cell transfer, instead of 4. a master that polls rxclav or paus- es 3 or 4 cycles before the end of the cell transfer may sample a false rxclav, and an overrun condition may occur. the dashed line in the timing diagram below depicts the actual rxclav ne- gation (two cycles before the end of the cell transfer instead of four cycles). the signals in the timing diagram are with respect to the master, so the tx interface is shown. workaround: 1. the master should not poll rxclav or pause a cell transfer 4 cycles before the end of a cell transfer. the master should poll 2 cycles before the end of the current cell or later. this can be achieved by introducing cell-to-cell polling (and transfer) delay, which is equal or larger than one cell transfer time. if this can be achieved, the impact on performance is minimal. 2. configuring atm only on fcc1 and setting fpsmr[tpri] ensures the highest pri- ority to fcc1 rx. in addition, for cpm usage lower then 80 percent (as reported by the cpm performance tool based on utopia maximal bus rate), the cpm perfor- mance is enough to guarantee that the rxfifo does not fill up. 0k40a 1k42a 2k42a 1k87m cpm111 fcc missing reset date added: 1/15/2004 description: the txbd may not close for the fcc in half-duplex 10baset ethernet. there may be a mismatch between the actual transmitted bd and the bd for which the status is updated. as a result, the status of one to three bds may not be updated. they appear to be ?ready? although the associated frames have been transmitted (assuming a frame per bd). workaround: use microcode patch provided by freescale. system number: 11064 fix plan: 0k40a 1k42a 2k42a 2k87m table 50. 2k87m errata errata number errata description applies to mask txclk txenb txclav txdata txsoc 1 2 3 4 50 52 53 54 55 56 57 58 51 clock cycles from end of cell: 54321 x h h2 p44 p45 p46 x x p47 p48 x
errata functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 79 cpm112 fcc missing reset at overrun date added: 12/19/2003 description: txbd may not be closed for fcc in half-duplex 10baset ethernet. there may be a mismatch between the actual transmitted bd and the bd for which status is updated. as a result, the status of one to three bds may not be updated, and they would appear "ready", although the associated frames have been transmitted (assuming a frame per bd). workaround: use microcode patch provided by freescale. system number: 11064, 11067 fix plan: n/a 0k40a 1k42a 2k42a 2k87m cpm113 incorrect return value from event register read (scc, spi, i 2 c, and smc) date added: 12/19/2003 description: when the event register is read while the scc, spi, i 2 c, or smc is active, it is sometimes read as 0, even though it has some bits set. workaround: system number: 11068 fix plan: 0k40a 1k42a 2k42a 2k87m cpm115 apc transmits unwanted idle cells date added: 12/19/2003 description: in heavily loaded atm applications, if the atm pace controller (apc) is config- ured for multiple priority levels and a burst of traffic for transmission is sustained long enough on the highest priority apc table, then an unwanted idle cell can be trasmitted on the lower priority apc tables when there are cells available in lower priority apc scheduling table for transmission. the transmission of the unwanted idles could cause the valid atm cells on lower-priority apc scheduling tables not to be transmitted. this transmission of unwanted idles can affect all atm channels that are not located in the highest-priority apc scheduling table. workaround: increase the size of lower-priority apc scheduling tables so they are large enough to absorb any burst or back-to-back bursts on the highest-priority apc scheduling table. other- wise, use the microcode patch available from freescale. system number: 11069 fix plan: 0k40a 1k42a 2k42a 2k87m cpm116 pointer 93 in partially filled (pfm) mode date added: 1/15/2004 description: in pfm mode, the pointer value of 93 is not generated, causing the loss of synchro- nization at the far end. also, when the pointer value of 93 is received, the synchronization is lost, which causes a loss of data and the resynchronization routine. workaround: use microcode patch provided by freescale. system number: 11912 fix plan: 0k40a 1k42a 2k42a 2k87m table 50. 2k87m errata errata number errata description applies to mask
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 80 freescale semiconductor errata cpm117 false address compression date added: 11/05/2004 description: if there are active aal0 channels and a crc-10 error has been received, vp-level address compression might have false results, which could lead to one of the following: wrong calculation of a vp pointer address cells might be falsely discarded as misinserted cells misidentification of misinserted cells (in cuab mode) this is a statistical error, which is conditional on the reception of aal0 cells with a crc-10 error. the probability of false address compression is directly correlated with higher cpm bit rate and longer system bus latency. while the false address compression is possible only if there are active aal0 channels, it may have an impact on all aal types. however, it cannot occur unless aal0 cells with crc-10 error have been received beforehand. workaround: use the microcode patch supplied by freescale. system number: 17129 0k40a 1k42a 2k42a 1k87m cpm118 aborted hdlc frame followed by a good frame date added: 7/11/2004 description: when an aborted hdlc frame is followed by a good frame, the receive data buffer may contain the data of the aborted frame followed by the data of the good frame. workaround: use the microcode patch provided by freescale. system number: 15905 fix plan: 0k40a 1k42a 2k42a 2k87m cpm119 ethernet collision occurs on the line 125 clocks after tx_en assertion date added: 7/11/2004 description: when an ethernet collision occurs on the line 125 clocks after tx_en assertion, late collision will be reported even though this is only 63 bytes into the frame instead of 64. when a collision occurs 124 cycles after tx_en assertion, no event is reported, the txbd is not closed, and transmission halts. retransmission behavior is correct for collisions occurring between asser- tion of tx_en and 123 clocks. workaround: use the microcode patch provided by freescale. system number: 15907 fix plan: 0k40a 1k42a 2k42a 2k87m cpm120 ss7_opt[fisu_pad] parameter has no effect on the number of flags between fisus date added: 12/22/2004 description: the ss7_opt[fisu_pad] parameter has no effect on the number of flags be- tween fisus. regardless of the value of this field, one flag will be present between back-to-back fisus. workaround: use the latest ss7 microcode package provided by freescale. system number: 18767 fix plan: none at this time. 2k87m table 50. 2k87m errata errata number errata description applies to mask
errata functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 81 cpm121 tdm data frame corruption date added: 11/05/2004 description: during a write to one of the si registers (gmr, amr, bmr, cmr, dmr) while one or more tdms are working, one data frame of a working tdm may become corrupted. workaround: work with the shadow ram when changing data and do not disable and then en- able the tdm. system number: 17460 0k40a 1k42a 2k42a 1k87m table 50. 2k87m errata errata number errata description applies to mask
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 82 freescale semiconductor bootloader program a bootloader program this appendix lists the boot program for mask set 2k87m of the msc8103. note: the first instruction in the boot code sets the stack address to 0x68000. in the event of a hard or soft reset, user data at this location is overwritten by the boot code. in addition, source code should not be bootloaded to this address due to corruption of the stack during the bootload program execution. ;/****************************************************************/ ;/* */ ;/* file : boot_code_reva.asm */ ;/* */ ;/* (c) copyright freescale inc, 2002. */ ;/* all rights reserved */ ;/* */ ;/* */ ;/* description: */ ;/* this file contains the msc8103 reva boot code as */ ;/* specified in the boot section of the reference manual. */ ;/* */ ;/* */ ;/* modifications from rev0: */ ;/* - host checksum fixed (erratum boot1) */ ;/* - sram base address is isb dependent (erratum boot2) */ ;/* - software watchdog handled in host code instead of */ ;/* disabled. */ ;/* - added i2c serial boot */ ;/* */ ;/****************************************************************/ stack_addr equ $68000 boot_bypass_add equ $0 ; banks mask0_a equ $00f0ff00 base0_a equ $00f0ff02 base0_d equ $00f00000 base1_a equ $00f0ff06 base_rom_address equ $00f80000 base_exeption_table equ $00f80000 external_mem_boot_table equ $fe000110 ; boot_rev_reg boot_rev_reg equ base_rom_address+$ffa0 ; host interface registers ; dsp side hcr equ base0_d+$0000 hpcr equ base0_d+$0020
bootloader program functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 83 hsr equ base0_d+$0040 hcvr equ base0_d+$0060 hotx equ base0_d+$0080 horx equ base0_d+$00a0 elire equ base0_d+$1c20 elirf equ base0_d+$1c28 ;the registers to be used are : ; d4,d5 for reading from the host fifo ; r3 for holding the block address ; d6 for holding the size ; d7 for holding the checksum ; d2 for holding the ~checksum ; d1,r6 for holding the immr ; r5 for holding the sram base mem ; d12,r15 for sw watchdog handling ; during the loading proces the checksum is calculated for the whole ; long and at the end of the block the two words in the calculated ; checksum are xored to generate the real checksum. ;---------- nmi0 (hdi16) offset 0xe00 ----- section nmi0 org p:$0e00+base_exeption_table nmi0 rte endsec ;---------- nmi1 (tea) offset 0xe40 ----- section nmi1 org p:$0e40+base_exeption_table nmi1 rte endsec ;---------- nmi2 (bus controller , memory write errors) offset 0xe80 ----- section nmi2 org p:$0e80+base_exeption_table nmi2 rte endsec ;---------- nmi3 (bus controller non aligned error) offset 0xec0 ----- section nmi3 org p:$0ec0+base_exeption_table nmi3 rte
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 84 freescale semiconductor bootloader program endsec ;---------- nmi4 (bus controller bus error) offset 0xf00 ----- section nmi4 org p:$0f00+base_exeption_table nmi4 rte endsec ;---------- nmi5(reserved) offset 0xf40 ----- section nmi5 org p:$0f40+base_exeption_table nmi5 rte endsec ;---------- nmi6 (reserved) offset 0xf80 ----- section nmi6 org p:$0f80+base_exeption_table nmi6 rte endsec ;---------- nmi7 (sic nmi,s/w wd,external nmi, parity) offset 0xfc0 ----- section nmi7 org p:$0fc0+base_exeption_table nmi7 rte endsec ;---------- illegal exeption offset 0x80 ---------- section illegal_exeption org p:$0080+base_exeption_table illegal_exeption rte endsec ;---------- debug exeption offset 0xc0 ---------- section debug_exeption org p:$00c0+base_exeption_table debug_exeption rte endsec
bootloader program functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 85 ;---------- overflow exeption offset 0x100 ---------- section overflow_exeption org p:$0100+base_exeption_table overflow_exeption rte endsec ;---------- auto nmi exeption offset 0x180 ---------- section auto_nmi_exeption org p:$0180+base_exeption_table auto_nmi_exeption rte endsec ;---------- auto ir exeption offset 0x1c0 ---------- section auto_ir_exeption org p:$01c0+base_exeption_table auto_ir_exeption rte endsec ;---------- in address 0 goto 0x1000 ------------- section start org p:$0000+base_rom_address start ; exeption stack pointer initialization move.l #base_exeption_table,vba; init vba move.l #stack_addr,r0 nop tfra r0,sp ; init esp ; stack initialization move.l #0,d3 move.l d3,(r0) jmp $1000+base_rom_address endsec ;----------------------- section boot org p:$1000+base_rom_address fmain move.l emr,d1
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 86 freescale semiconductor bootloader program extractu #2,#17,d1,d3 ;get ee4,ee5 -> d3 nop cmpeq.w #$3,d3 jt to_boot_bypass move.l emr,d1 extractu #3,#19,d1,d3 ; d3 xor 3'b100 to recover original isb eor #$4,d3.l nop move.l d3,d13; added for serial boot jmp find_siubase return_find_siu ; sram init jmp sram_init return_sram_init ; initialize elire move.w #$8000,d0 nop move.w d0,elire ; initialize elirf move.w #$0008,d0 nop move.w d0,elirf ;check the scmr to see which upm routine to load move.l (r6+$c88),d1 ;scmr,d1 ; extract the busdf from scmr extractu #4,#20,d1,d3 jmp upmc_init check_boot move.l emr,d1 ;get ee4,ee5 -> d3 extractu #2,#17,d1,d3 nop cmpeq.w #$0,d3 jt external_memory cmpeq.w #$1,d3 jt from_host cmpeq.w #$2,d3;added for serial boot jt from_serial cmpeq.w #$3,d3;added for serial boot jt to_boot_bypass stop external_memory ;d3 <- isb[0,1,2] extractu #3,#19,d1,d3 ; d3 xor 3'b100 to recover original isb eor #$4,d3.l ;r3 <- d3
bootloader program functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 87 move.l d3,r3 nop ; find immr from isb ;r3 *= 4 so the offset will be in long instead of bytes ;r3 = r3<<2 asl2a r3 ;put the address of the external memory boot table in r4 move.l #external_mem_boot_table,r4 nop adda r4,r3 nop ;move the address from the table into r3 move.l (r3),r3 nop ;jump to that address jmp r3 to_boot_bypass jmp boot_bypass_add nop from_host ; software watch dog is not disabled ; it will be handled in the load_from_fifo routine if it is enabled move.l #$0,d15;clear d15, software watchdog is not enabled move.l (r6+$4),d1;get sypcr value bmtsts #$0004,d1.l jf hdi_en nop move.l d15,r15 ; clear watchdog handle counter move.l #$1,d15; indicate software watchdog enabled move.l #$0100,r15; initialize watchdog handle counter ;set the hen bit in hpcr hdi_en move.w hpcr,d3 or #$0080,d3.l move.w d3,hpcr ;get the 8bit bit from hpcr ( which is in d3 ) ;if (8bit ) goto load_8bit else goto load_16bit bmtsts #$0040,d3.l jt load_8bit jmp load_16bit load_last_long_2_16 ;if the size left to load is only 2 words ( 4 bytes) ;and the mode is 16-bit so every load action is of 4 words ;in this case the load action already loaded the checksum ;and the ~checksum, so it is a special case which needs handling ;by itself jsr load_from_fifo
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 88 freescale semiconductor bootloader program ;move the last 2 words to their address (which is kept in r3) move.l d4,(r3) adda #$4,r3 ;write checksum , ~checksum at the and of the block move.l d5,(r3) ;calculate the checksum of these words eor d4,d7 ;calculate ~checksum -> d2 ;get the real checksum from d7 and ;get it into d7.l as explained in the beggining of the file ;d2 = (0xffff0000 & d7)>>16 extractu #16,#16,d7,d2 ;d2 = d2 & 0x0000ffff and #$0000ffff,d2,d2 ;d7 = d7 & 0x0000ffff and #$0000ffff,d7,d7 ;d7 = d7 ^ d2 = checksum eor d2,d7 ;d2 = (~d7 & 0x0000ffff) = ~checksum not d7,d2 and #$0000ffff,d2,d2 ;get loaded checksum , ~checksum from d5 ;get checksum into d4 extractu #16,#16,d5,d4 and #$0000ffff,d4,d4 ;delete the checksum from d5 and #$0000ffff,d5,d5 ;if ( ~checksum_loaded |= ~checksum_calculated ) goto set sticky bit cmpeq d5,d2 nop iff jsr set_sticky_bit ;if ( checksum_loaded |= checksum_calculated ) goto set sticky bit cmpeq d4,d7 nop iff jsr set_sticky_bit ;goto loading the next block ;goto load_16bit load_16bit ;d7 = checksm =0 , clear the calculated checksum register move.l #0,d7 ;load the size and address jsr load_from_fifo ;move the size into d6 move.l d4,d6 ;move the address into r3 move.l d5,r3 ; should be calculated on data and address also
bootloader program functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 89 eor d4,d7 eor d5,d7 ; check if the finished (hf4) bit is set ,if it is set clear it ; and the sticky bit .( it means there was an error and ; the blocks are being loaded for the second time move.w hcr,d4 bmtsts.w #$8000,d4.l jf continue_loading_16 move.w hcr,d4 and #$6fff,d4.l move.w d4,hcr continue_loading_16 ;if (size == 0 ) in the beggining of a block it means no more blocks ;then jump to the address loaded in r3 (from d5 ) tsteq d6 jt end_of_loading_16 load_loop_16 ;if (size ==2 ) it is a special case so goto load_last_long_2_16 move.l #$00000002,d4 cmpeq d4,d6 jt load_last_long_2_16 ;load 2 data words jsr load_from_fifo ;load the first 2 data words (4 bytes) to the address move.l d4,(r3) ;increment the address by 4 bytes adda #$4,r3 ;load the second 2 data words (4 bytes) to the address move.l d5,(r3) ;increment the address by 4 bytes adda #$4,r3 ;calculate_checksum eor d4,d7 eor d5,d7 ;decrease the size by 4 words sub #$4,d6 ;jump to loading the next words jmp load_loop_16 load_8bit move.l #0,d7 ; un-initialized dalu register. ;load the size into d6 jsr load_from_fifo
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 90 freescale semiconductor bootloader program ; check if the finished bit (hf4)is set ,if it is set clear it ; and the sticky bit .( it means there was an error and ; the blocks are being loaded for the second time move.w hcr,d6 bmtsts.w #$8000,d6.l jf continue_loading_8 move.w hcr,d6 and #$6fff,d6.l move.w d6,hcr continue_loading_8 eor d5,d7 ;checksum is calculated on size move.l d5,d6 ;if (size == 0) it means the last block was loaded ;so goto end_of_loading tsteq d6 jt end_of_loading ;load the address jsr load_from_fifo move.l d5,r3 eor d5,d7 ;checksum is calculated on address load_loop_8 ;load data word jsr load_from_fifo move.l d5,(r3) ;add 4 bytes to the address adda #$4,r3 ;calculate_checksum d7 = d7 ^ d5 eor d5,d7 ;subtract 2 words from the size sub #$2,d6 ;if ( size | = 0) go to load_loop_8 tsteq d6 jf load_loop_8 ;get the checksum into d7.l ;d2 = (0xffff0000 & d7)>>16 extractu #16,#16,d7,d2 ;d2 = d2 & 0x0000ffff and #$0000ffff,d2,d2 ;d7 = d7 & 0x0000ffff and #$0000ffff,d7,d7 ;d7 = d7 ^ d2 eor d2,d7 ;d2 = (~d7 & 0x0000ffff) = ~checksum not d7,d2 and #$0000ffff,d2,d2 ;load the checksum ,~checksum jsr load_from_fifo ;get ~checksum into d4 extractu #16,#16,d5,d4 ;delete the ~checksum from d4
bootloader program functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 91 and #$0000ffff,d5,d5 ;if ( checksum_loaded |= checksum_calculated ) goto set sticky bit cmpeq d5,d2 nop iff jsr set_sticky_bit ;if ( ~checksum_loaded |= ~checksum_calculated ) goto set sticky bit ;clean d4.h and #$0000ffff,d4,d4 cmpeq d4,d7 ; d4,d7 contain checksum nop iff jsr set_sticky_bit ;goto load the next block jmp load_8bit end_of_loading_16 jsr load_from_fifo ;get the checksum into d7.l ;d2 = (0xffff0000 & d7)>>16 extractu #16,#16,d7,d2 ;d2 = d2 & 0x0000ffff and #$0000ffff,d2,d2 ;d7 = d7 & 0x0000ffff and #$0000ffff,d7,d7 ;d7 = d7 ^ d2 eor d2,d7 ;d2 = (~d7 & 0x0000ffff) = ~checksum not d7,d2 and #$0000ffff,d2,d2 ;get checksum into d4 extractu #16,#16,d5,d4 ;delete the checksum from d5 and #$0000ffff,d5,d5 ;if ( ~checksum_loaded |= ~checksum_calculated ) goto set sticky bit cmpeq d5,d2 ;d5 and d2 contain ~checksum nop iff jsr set_sticky_bit ;clean d4.h and #$0000ffff,d4,d4 ;if ( checksum_loaded |= checksum_calculated ) goto set sticky bit cmpeq d4,d7 nop iff jsr set_sticky_bit ;set hf4 bit in hcr to show that loading is finished move.w hcr,d6 or #$00008000,d6.l move.w d6,hcr ;check if the checksum bit is set ( hf3 in hsr (hsr[3] ) move.w hsr,d6 and #$00001000,d6,d6
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 92 freescale semiconductor bootloader program ;check if the sticky bit is set ( hf7 in hcr (hcr[3]) ) move.w hcr,d4 and #$00001000,d4,d4 ;if both of the flags are set start the loading again and d4,d6 tsteq d6 jf from_host ;if everything is ok jump to the address in r3 jmp r3 end_of_loading ;load the destination address into r3 jsr load_from_fifo move.l d5,r3 eor d5,d7 jsr load_from_fifo ; reads 0 jsr load_from_fifo ; reads checksum to d5 ;get the checksum into d7.l ;d2 = (0xffff0000 & d7)>>16 extractu #16,#16,d7,d2 ;d2 = d2 & 0x0000ffff and #$0000ffff,d2,d2 ;d7 = d7 & 0x0000ffff and #$0000ffff,d7,d7 ;d7 = d7 ^ d2 eor d2,d7 ;d2 = (~d7 & 0x0000ffff) = ~checksum not d7,d2 and #$0000ffff,d2,d2 ;get ~checksum into d4 extractu #16,#16,d5,d4 ;delete the ~checksum from d5 and #$0000ffff,d5,d5 ;if ( checksum_loaded |= checksum_calculated ) goto set sticky bit cmpeq d5,d2 nop iff jsr set_sticky_bit ;clean d4.h and #$0000ffff,d4,d4 ;if ( ~checksum_loaded |= ~checksum_calculated ) goto set sticky bit cmpeq d4,d7 nop iff jsr set_sticky_bit ;set hf4 bit in hcr to show that loading is finished move.w hcr,d6 or #$8000,d6.l move.w d6,hcr
bootloader program functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 93 ;check the check sticky bit is set ( hf3 in hsr (hsr[3) ) move.w hsr,d6 and #$00001000,d6,d6 ;check if the sticky bit is set ( hf7 in hcr(hcr[3]) ) move.w hcr,d4 and #$00001000,d4,d4 ;if both of the flags are set start the loading again and d4,d6 tsteq d6 jf from_host nop ; jump to the destination address jmp r3 load_from_fifo tsteq d15 ; check flag if watchdog disabled jt load_no_wd load_wd deceqa r15 nop ift jsr watchdog_handle hsr_read move.w hsr,d4 bmtsts.w #$0001,d4.l jf load_wd nop jmp read_fifo nop load_no_wd ;if the host is empty wait for it to fill move.w hsr,d4 bmtsts.w #$0001,d4.l jf load_no_wd ; the host is not empty so load 8 bytes from it read_fifo move.l #horx,r0 nop move.2l (r0),d4:d5 rts ; set the sticky bit (hf7) if there is an error in loading the program set_sticky_bit ;set the hf7 bit in hcr move.w hcr,d6 or #$00001000,d6.l move.w d6,hcr rts watchdog_handle move.l #$0100,r15 move.w #$556c,d12 move.w d12,(r6+$e) ;write $556c to swsr move.w #$aa39,d12 move.w d12,(r6+$e) ;write $aa39 to swsr rts
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 94 freescale semiconductor bootloader program find_siubase ;read immr using siureg1 move.l #$00f8ffc0,r7;move address of immr (using siureg1) into d9 nop move.l (r7),d1;read immr into d1 nop extractu #$20,#0,d1,d1;remove the extend bits nop and #$ffff0000,d1,d1;leave only isb bits on immr move.l d1,d9 ;added for serial boot ;d9 gets the immr value inc.f d1 ; d1+$10000->d1 jmp return_find_siu sram_init move.l d1,r6 move.l #$00000200,d1; base address for bank 10 move.l #$00000100,d2; delta/2 imac d2,d3,d1; (d1+d3.l*d2.l)->d1 aslw d1,d1 ; d1<<16 move.l #$01f00000,d0; offset 2 (for bank 11) aslw d3,d2 ; multiply d3 by 0x10,000 add d2,d0,d0 move.l d1,r5 ; bmset #$00c1,d1.l move.l #$fff80000,d7 move.l d7,(r6+$154); set or10 move.l d1,(r6+$150); set br10 ; gpcm_init move.l #$ffff0000,d1; set or11 mask 64 kb bmset #$0021,d0.l; changed the machine select to gpcm. move.l d1,(r6+$15c); set or11 mask 64 kb move.l d0,(r6+$158); set br11 to $01f0_0000 jmp return_sram_init upmc_init ; -------------- read single ------------------------------------- move.l #$90051240,d7 move.l d7,(r6+$178) ; move.l #$00030040,d7 move.l d7,(r6+$188) ; cmpeq.w #$2,d3 jf continue_upmc1 move.w #$0,(r5) ; move.l #$00030040,d7 move.l d7,(r6+$188) ; continue_upmc1 move.w #$0,(r5) ; move.l #$00030045,d7 move.l d7,(r6+$188) ;
bootloader program functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 95 move.w #$0,(r5) ; ; -------------- read burst ------------------------------------- move.l #$90051248,d7 move.l d7,(r6+$178) ; move.l #$00030c48,d7 move.l d7,(r6+$188) ; move.w #$0,(r5) ; move.l #$00030c4c,d7 move.l d7,(r6+$188) ; move.w #$0,(r5) ; move.l #$00030c4c,d7 move.l d7,(r6+$188) ; move.w #$0,(r5) ; move.l #$00030044,d7 move.l d7,(r6+$188) ; move.w #$0,(r5) ; move.l #$00030045,d7 move.l d7,(r6+$188) ; move.w #$0,(r5) ; ; -------------- write single ------------------------------------- move.l #$90051258,d7 move.l d7,(r6+$178) ; move.l #$00000040,d7 move.l d7,(r6+$188) ; cmpeq.w #$2,d3 jf continue_upmc2 move.w #$0,(r5) ; move.l #$00000040,d7 move.l d7,(r6+$188) ; continue_upmc2 move.w #$0,(r5) ; move.l #$00000045,d7 move.l d7,(r6+$188) ; move.w #$0,(r5) ; ; -------------- write burst ------------------------------------- move.l #$90051260,d7 move.l d7,(r6+$178) ; move.l #$00000c48,d7 move.l d7,(r6+$188) ; move.w #$0,(r5) ; move.l #$00000c4c,d7 move.l d7,(r6+$188) ; move.w #$0,(r5) ;
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 96 freescale semiconductor bootloader program move.l #$00000c4c,d7 move.l d7,(r6+$188) ; move.w #$0,(r5) ; move.l #$00000044,d7 move.l d7,(r6+$188) ; move.w #$0,(r5) ; move.l #$00000045,d7 move.l d7,(r6+$188) ; move.w #$0,(r5) ; ; -------------- exception ------------------------------------- move.l #$9005127c,d7 move.l d7,(r6+$178) ; move.l #$ff000001,d7 move.l d7,(r6+$188) ; move.w #$0,(r5) ; ; -------------- resume normal operation ------------------------- move.l #$80011240,d7 move.l d7,(r6+$178) ; jmp check_boot ;serial boot code here ;********************************************************* txb equ $2160 ;tx buffer pointer rxb equ $2170;rx buffer pointer timeout equ $80000 ;time out till system is consider dead serbit16 equ $1000 ; ;i2c parameter ram i2c_base equ $8afc i2c_base_val equ $3e00 ;to these rbase equ $3e00 rbaseval equ$3e50 tbaseval equ$3e40 rtbaseval equ $3e503e40 rfcr equ $3e04 rstate equ $3e08 rptr equ $3e0c rbptr equ $3e10 rtemp equ $3e14 tstate equ$3e18 tptr equ $3e1c tbptr equ $3e20 ttemp equ $3e24
bootloader program functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 97 debugptr equ $3ea0 debugend equ $3ef0 ; backup of registers sccrb equ $3f00 podrbb equ$3f04 psorbb equ$3f08 pparbb equ $3f0c pdirbb equ $3f10 ; sypcr equ$0004 swsr equ $000e sccr equ $0c80 cpcr equ $19c0 ;i2c register i2mod equ $1860 i2add equ$1864 i2brg equ $1868 i2cer equ $1870 i2cmr equ $1874 i2com equ $186c ;pb regs podrb equ$0d2c psorb equ$0d28 pparb equ $0d24 pdirb equ $0d20 pdatb equ$0d30 pdatc equ$0d50 i2modval equ$001a;gcd=1, flt=1 , pdiv = 01 i2modvale equ$001b;gcd=1, flt=1 , pdiv = 01 , en = 1 i2brgval equ$0007 arslaveaddress equ $af000000;aligned read slave address awslaveaddress equ $ae000000;aligned write slave address ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;reserved register: ; d5 : the address for read_bd function (byte shifted ) ; d7 : the rx buffer lenght for read_bd function ; d8 : ; d9 : immr - setted by previous boot_code ; d10: block counter ( count the numer of loaded blocks )
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 98 freescale semiconductor bootloader program ; d12: used for watchdog handler function. ; d14: tx buffer address, for read_db function. ; r2 : pointer to address of block data on eeprom ; r5 : the rx buffer pointer for read_bd function ; r6 : immr + $0001_0000 ; r7 : immr ; ;the follow registers were initiated by the previous code (boot_code_reva1. ) ; d13:contain the isb bits ; d9 :immr ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; ------------------------------------------------------------------ ; ----------------- serial boot code start here ------------------ ; ------------------------------------------------------------------ from_serial move.l d9,r7 ;d9&r7 will have always immr value move.l r7,d11 move.l #$10000,d12 add d11,d12,d11 move.l d11,r6;r6<-immr+$10000 for registers access ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; configure i2 register & ; parameter ram ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; move.l d9,r3 ;r3 <- immr bmset #i2c_base,r3.l;r3 receive i2c page base address ;sw watchdog move.l #$0,d11;clear d11, software watchdog is not enabled move.l (r6+$4),d12;get sypcr value bmtsts #$0004,d12.l jf init_ nop move.l d11,r15 ; clear watchdog handle counter move.l #$1,d11; indicate software watchdog enabled move.l #$0100,r15 ; initialize watchdog handle counter ;initiate i2c_base init_ move.w #i2c_base_val,d4 nop ;inserted due to restriction 6.4.4.a.2 move.w d4,(r3);save d4 into i2c_base ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;initiate parameter ram move.l #rtbaseval,r1 ;rbase=3e50,tbase=3e40 nop ;due to restriction 6.4.4.a.2 move.l r1,(r7+rbase);$00 move.l #$1212ff00,r1 ;rfcr=12(use local bus),tfcr=12,mrlbr=ff00
bootloader program functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 99 nop ;due to restriction 6.4.4.a.2 move.l r1,(r7+rfcr) ;$04 move.l #$00000000,r1 ;rstate nop ;due to restriction 6.4.4.a.2 move.l r1,(r7+rstate);$08 move.l r1,(r7+rptr) ;$0c move.l r1,(r7+rbptr);$10 move.l r1,(r7+rtemp);$14 move.l r1,(r7+tstate);$18 move.l r1,(r7+tptr) ;$1c move.l r1,(r7+tbptr);$20 move.l r1,(r7+ttemp);$24 move.l #$10000,d1 nop ;due to restriction 6.4.4.a.2 add d1,d9,d4 ;d4 receive immr +1_0000 nop ;due to restriction 6.4.4.a.2 move.l d4,r6 ;r6 <-immr +1_0000 ;initiate i2c command - page = 01010,code=01011 move.l #$29610000,r1 nop move.l r1,(r6+cpcr);write the cmd to cpcr ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;save registers in the backup area of dp ram ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; move.l (r6+sccr),r1 nop move.l r1,(r7+sccrb) move.l (r6+podrb),r1 nop move.l r1,(r7+podrbb) move.l (r6+psorb),r1 nop move.l r1,(r7+psorbb) move.l (r6+pparb),r1 nop move.l r1,(r7+pparbb) move.l (r6+pdirb),r1 nop move.l r1,(r7+pdirbb) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; initiate sccr to 01 -> divide by 16 move.l #1,r1 move.l r1,(r6+sccr) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;initiate io port ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; configure port b scl=pb18,sda=pb19 move.l #$00003000,r1 nop ;due to restriction 6.4.4.a.2
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 100 freescale semiconductor bootloader program move.l r1,(r6+podrb); podrb[18,19]=1 move.l r1,(r6+psorb); psorb[18,19]=1 move.l r1,(r6+pparb); move.l #$00000000,r1 nop ;due to restriction 6.4.4.a.2 move.l r1,(r6+pdirb); ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;initiate i2c registers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; move.w #$0,r1 move.b r1,(r6+i2mod);clear i2mod move.b r1,(r6+i2cmr);disable all interrupt move.w #$ec,r1 move.b r1,(r6+i2add);slave address= 00 ( optional ) move.w #$0017,r1 move.b r1,(r6+i2cer) ;clear all previous events move.w #i2modval,r1 move.b r1,(r6+i2mod);i2mod[gcd]=1,[flt]=1 move.w #i2brgval,r1 move.b r1,(r6+i2brg) ;i2brg[div]=6 move.w #$0001,r1 move.b r1,(r6+i2com) ;i2com[m/s]=1 ( master mode ) move.w #i2modvale,r1 move.b r1,(r6+i2mod);set i2mo[en] ;********************************* ;sram base moved to r7 due to register usage ;******************************** move.l r5,(r5) nop move.l (r5),r7 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; initiate debug area at immr + debug pointer ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; move.l #debugptr,d10 ; add d9,d10,d10;d10 <- ptr to debug area move.l d10,r1;r1 <- ptr to debug area add #$4,d10 ;d10 <- ptr to empty space in debug area nop move.l d10,(r1);save the the ptr in r1 move.l d10,r1 ;move empty ptr to r1 ; this lines will move a empty pattern ( a5 ) ; to all the debug area move.w #$a5a5,d10;d10 receive empty pattern iloop move.b d10,(r1)+;save empty pattern in r1 and increment r1 nop ;added due to restriction move.l r1,d8;move r1 to d8 nop ;added due to restriction
bootloader program functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 101 extractu #$f,#0,d8,d8 ;leave only offset in d8 nop ;added due to restriction cmpeq.w #debugend,d8;compare if end of debug jf iloop ;if not jmp to the loop nop ;added due to restriction ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; calculate table address & ; get the code address ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; move.l d13,d5 ; d5 receive isb move.l #$0,d10 ; reset the blocks counter ( d10 ) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; read first block address ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;d5 <- d5 x 2 + byte shift left asll #$9,d5 ;d5 <- address(1 byte shifted ) move.l #$2,d7;d7 <- rx bd lenght move.l #txb,d4;prepare tx buffer address in d14 move.l r5,d14;r5 holds sram base address nop add d4,d14,d14;add sram base move.l #rxb,r5 ;r5 <-rx buffer ofset from sram move.l r7,d4 ;d4 <-sram base bsr read_bd ;in the read_bd routine ,the start of code address ( 2 bytes ) ;was read to the rx buffer at address rxb move.w (rxb),d5;d5 receive the code start address bmclr #$ffff,d5.h;clear unreaded upper bits move.l d5,d8;back d5 it into d8 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; prepare for read first block header ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;d5 <- d5 x 2 + byte shift left asll #$8,d5 ;d5 <- address(1 byte shifted ) move.l #$8,d7;d7 <- header lenght(4 words) ; calculate the address for head at dpram move.l #rxb,d2 ; d2<- block header (ofset from immr) nop ;due to restriction 6.4.4.a.2 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; get 4 first word ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; get4fword move.l d2,r5; r5<-head pointer ( rxb ) move.l #$8,d7; d7 <- header lenght(4 words) bsr read_bd ; call read_bd to read the first 4 words ; read the block header data move.l r5,d6; d6<-head pointer offset nop ;due to restriction 6.4.4.a.2 add d4,d6,d6; d6<-head pointer offset + ramptr move.l d6,r8; r8<-head pointer offset + ramptr nop ;due to restriction 6.4.4.a.2 move.w (r8),d7;d7 <- cs enabled bit | block size
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 102 freescale semiconductor bootloader program extractu #$e,#0,d7,d7 ;remove the extend bits and cs ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; if block size == 0 goto boot_loaded ( end ) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; tsteq d7 ;compare d7 to 0 jt boot_loaded;if d7 = 0->jmp to boot loaded nop ;due to restriction 6.4.4.a.3 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; read block data ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; move.l (r8+$4),r5;address to save the data on dpram (offset from sram ) move.l d8,d5 ;d5<-block data address on seeprom nop ;due to restriction 6.4.4.a.2 add #$8,d5 ;increment d5 so it points to data (first 8 bytes = header ) asll #$8,d5 ;byte shift d5 ( prepare for read_bd) read_block move.l #$0,d0 ;reset status bit in d0 read_block2 move.l r7,d4 bsr read_bd move.l d2,r4;r4<-head pointer nop ;due to restriction 6.4.4.a.2 move.w (r4),d8;d8<- cse | block size ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;checksum enabled ???? ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; bmtsts #$8000,d8.l; test with cs bit is setted jt calc_cs ;if checksum enable jump to calc cs nop ;;due to restriction 6.4.4.a.3 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; prepare next block address ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; preparenextbadd add #$1,d10 ;increment the bd counter move.w (r4+$2),d8;d8<- next block address move.l d8,d5;restore address from d8 asll #$8,d5 ;d5 <- address for next block(1 byte shifted ) jmp get4fword;jmp to get 4 first words nop ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;start boot execution ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; boot_loaded move.l #$80,d0 ;set boot loaded flag on d0 move.l (r8+$4),r3;r3 receive boot start address ; reset all i2c parameter to their default value move.l #$0,r1 move.b r1,(r6+i2mod);clear i2mod move.b r1,(r6+i2add);slave address= 00 ( optional )
bootloader program functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 103 move.b r1,(r6+i2cmr);disable all interrupt move.b r1,(r6+i2brg) ;i2brg[div]=6 move.b r1,(r6+i2com) ;i2com[m/s]=1 ( master mode ) move.w #$0017,r1 move.b r1,(r6+i2cer) ;clear all previous events ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;reload saved registers values from the backup area of dp ram ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; move.l d9,r7 nop move.l (r7+sccrb),r1 nop move.l r1,(r6+sccr) move.l (r7+podrbb),r1 nop move.l r1,(r6+podrb) move.l (r7+psorbb),r1 nop move.l r1,(r6+psorb) move.l (r7+pparbb),r1 nop move.l r1,(r6+pparb) move.l (r7+pdirbb),r1 nop move.l r1,(r6+pdirb) jmp end_ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; end of main code flow ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; calc_cs ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;calculate checksum ;for this we will use the follow register ; d1 : calculated cs ; d6 : words count ; r1 : adddress of word to be read ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; move r5,d6 nop ;due to restriction 6.4.4.a.2 add d4,d6,d6;d6<-first rx buffer pointer nop ;due to restriction 6.4.4.a.2 move.l d6,r1 ;r1 receive the address of first word move.l (r4),d1 ;start xor with getting 1'st 2 words of block move.l (r4+4),d6 ;get 2'nd 2 words eor d6,d1 ;xor with previous value
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 104 freescale semiconductor bootloader program move.l #$0,d6 ;reset the word count cs_loop move.l (r1)+,d3;read long data into d3 add #$4,d6 cmpeq d6,d7 ;if d6 = d7 ->last block word ( cs ) jt calc_rchecksum; then jump to calc_checksum nop ;due to restriction 6.4.4.a.3 eor d3,d1 ; else cs <- ( cs xor data ) jmp cs_loop nop ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; calc_rchecksum aslw d1,d6 ;shift left word d1 into d6 eor d1,d6 extractu #$20,#0,d6,d6;remove the extend bits bmclr #$ffff,d6.l;leave only the checksum on d6.h asrw d6,d1 ;move it (word shift right) to d1 not d1.l ;obtain inverted cs (cs_b) on d1 add d1,d6,d6;obtain cs|cs_b on d6 extractu #$20,#0,d3,d3;remove the extend bits ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; checksum ok ? ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; cmpeq d6,d3 ;compare to received cs jt preparenextbadd;if equal jump to received bd nop ;due to restriction 6.4.4.a.3 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;got a cs error ;if this is the first cs error for this bd , set flag and retry ; else jmp to cs error ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; bmtsts #$0001,d0.l;test with previous cs error ocurr ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; first error ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; jt cs_error;if yes jump to cs error routine nop ; due to restriction 6.4.4.a.3 bmset #$0001,d0.l;set cs fail flag jmp read_block2;retry to read the block ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; set bit 1 in d0 ( to indicate a cs error) and abort cs_error bmset #$0002,d0.l;set cs error flag jmp reset ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;************************************************** read_bd ;this routine will read a bd
bootloader program functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 105 ;this routine will create 2 tx bd and one rx bd that receive the data ;before enter these routine the registers must be setted as follow: ; d9 : immr ; d4 : rx buffer pointer base (sram base) ; d5 : the address of eeporm to be read (shifted 1 byte) ; d14: tx buffer address ; left, e.g add=$4 -> d5 = $0400) ; d7 : the lenght for rx bd ; r6 : immr + $1_0000 ; r5 : rx buffer pointer offset ;corrupted registers: ; d1,d3,d6 ,r0,r1,r3 ;************************************************** retry move.w #$0017,r1 move.b r1,(r6+i2cer) ;clear all previous events ;prepare the 2 tx & 1 rx bd's to read 2 bytes from add8ess at d5 move.l #tbaseval,d1 ; d1<-tbase nop ;due to restriction 6.4.4.a.2 add d9,d1,d1; d1<-tx bd ptr move.l d1,r0 ; r0<-tx bd ptr ;************************************************** ;prepare 2 tx & 1 rx bd ;************************************************** ; first tx bd move.l #$84000003,d1;bd status(r=1,i=1,l=0,s=1)|data lenght = 3 move.l d1,(r0) move.l d14,(r0+$4) ;tx buffer address ; write tx buffer data move.l d14,r3 ;r3 receive the tx buffer ptr move.l #awslaveaddress,d6 extractu #$20,#0,d6,d6;remove the extend bits add d5,d6,d6 ;d5=slave address | address word move.l d6,(r3) ; 2nd tx bd move.l #$bc000001,d3;bd status(r=1,i=1,w=1,l=1,s=1)|lenght = 1 add d7,d3,d3;set lenght = d7 + 1 move.l d3,(r0+$8) move.l d14,d6 add #$4,d6 ; d6<-2nd tx buffer pointer move.l d6,(r0+$c) ; write tx buffer data for second buffer move.l #arslaveaddress,d6 extractu #$20,#0,d6,d6;remove the extend bits move.l d6,(r3+4) ;prepare the rx bd move.l #rbaseval,d1 ; d1<- rbase add d9,d1,d1; d1<- bd ptr nop ;due to restriction 6.4.4.a.2 move.l d1,r1 ; r1<- bd ptr nop ;due to restriction 6.4.4.a.2
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 106 freescale semiconductor bootloader program move.l #$b8000000,d1;bd status(e=1,w=1,i=1,l=1)|data lenght = 0 nop ;due to restriction 6.4.4.a.2 move.l d1,(r1) ;write bd status + lenght move r5,d1 ;d1 receive buffer ptr offset nop add d1,d4,d1; added buffer base to d1 nop move d1,r3 nop ;due to restriction 6.4.4.a.2 move.l r3,(r1+$4);write rx buffer pointer ;************************************************** ;set start on i2com ;************************************************** i2com_ move.w #$8181,r3 move.b r3,(r6+i2com) ;i2com[str]=1 => start transmission move.l r6,d6 move.l #i2cer,d1 add d1,d6,d6 move.l d6,r3 ; r3<-i2cer adrress move.l #timeout,d1 read_i2cer move.l #serbit16,d15 ;************************************************** ; we insert a delay here in order to have ; less bus activity ;************************************************** ser_cnt sub#$1,d15 tsteq d11; check flag if watchdog disabled jt tst_no_wd deceqa r15 nop ift jsr watchdog_handle tst_no_wd tsteqd15 jf ser_cnt nop ;;decrement counter if zero goto dead_i2cer sub #$1,d1 tsteq d1 jt dead_i2cer nop ; due to restriction 6.4.4.a.3 move.b (r3),d6 ;read i2cer nop cmpeq.w #$0000,d6 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; i2cer == 0 ??
bootloader program functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 107 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; jt read_i2cer;if i2cer =0 => read again nop ;due to restriction 6.4.4.a.3 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; bd & i2cer ok ??? ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; the following lines test bd and i2cer ; to check that we received data correctly. ; if not, we will retry if possible or abort ( depending on error type ) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; bmtsts #$04,d6.l;test bsy bit jt bsyerror;if true abort nop ;due to restriction 6.4.4.a.3 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; move.w (r0),d3 ;read the bd status of the 1st txbd nop bmtsts #$01,d3.l;test colision bit jt colision;if true retry nop ;due to restriction 6.4.4.a.3 bmtsts #$04,d3.l;test nak bit jt nak ;if true abort nop ;due to restriction 6.4.4.a.3 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; move.w (r0+$8),d3 ;read the bd status of the 2nd txbd nop bmtsts #$01,d3.l;test colision bit jt colision2;if true retry nop ;due to restriction 6.4.4.a.3 bmtsts #$04,d3.l;test nak bit jt nak ;if true abort nop ;due to restriction 6.4.4.a.3 cmpeq.w #$0003,d6;if not i2cer[txb]=1,i2cer[rxb]=1 jf read_i2cer;read again nop ;due to restriction 6.4.4.a.3 move.w (r1),d3 ;read the bd status of the rxbd ( r1 contain rx bd ptr ) nop cmpeq.w #$3800,d3 jf read_i2cer nop ;due to restriction 6.4.4.a.3 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; write to debug area at immr + debug pointer ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; wdebug move.l #debugptr,d3
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 108 freescale semiconductor bootloader program add d9,d3,d3;d3 <- ptr to debug area nop move.l d3,r1;r1 receive d13 nop ;due to restriction move.l (r1),d3 ;d3 receive available address on debug area move.l d3,r0;r0 receive available address on debug area ; check with end of debug area move.l r0,d6 nop extractu #$f,#0,d6,d6 ;remove the extend bits and cs nop cmpeq.w #debugend,d6 jt wdebugend;if end of debug area jmp to end of debug nop ;;;;;;;;;;; move.w #0,d6 move.b d6,(r0)+;write 0 and increment d3 nop move.l r0,(r1) wdebugend nop return_rts ;return from sub routine ;************************************************** ; end of read_bd function ;************************************************** ;************************************************** dead_i2cer move.l #$deadead,d0 reset move.l #$0,r1 ; reset port b scl=pb18,sda=pb19 move.l r1,(r6+podrb) move.l r1,(r6+psorb) move.l r1,(r6+pparb) move.l r1,(r6+pdirb) debug colision colision2
bootloader program functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 109 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; write to debug area at immr + debug pointer ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; move.l #debugptr,d3 add d9,d3,d3;d3 <- ptr to debug area nop move.l d3,r1;r1 receive d13 nop ;due to restriction move.l (r1),d3 ;d3 receive available address on debug area move.l d3,r0;r0 receive available address on debug area ; check with end of debug area move.l r0,d6 nop extractu #$f,#0,d6,d6 ;remove the extend bits and cs nop cmpeq.w #debugend,d6 jt wdebugend2 nop ;;;;;;;;;;; move.w #1,d6 move.b d6,(r0)+;write 0 and increment d3 nop move.l r0,(r1) wdebugend2 restart ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; close rx bd command routine + wait ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; move.l #$29610007,r1 nop move.l r1,(r6+cpcr);close bd command - page = 01010,code=01011 ; ***wait for command flag to be clear wait move.l (r6+cpcr),d1 nop bmtsts #$0001,d1.h; test with cs bit is setted jt wait ;if flag is still setted goback to wait nop ;due to restriction 6.4.4.a.3 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;initiate parameter ram move.l #rtbaseval,r1 ;rbase=3e50,tbase=3e40 nop ;due to restriction 6.4.4.a.2 move.l r1,(r7+rbase);$00 move.l #$1212ff00,r1 ;rfcr=12(use local bus),tfcr=12,mrlbr=ff00 nop ;due to restriction 6.4.4.a.2
functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 110 freescale semiconductor bootloader program move.l r1,(r7+rfcr);$04 move.l #$00000000,r1 ;rstate nop ;due to restriction 6.4.4.a.2 move.l r1,(r7+rstate);$08 move.l r1,(r7+rptr);$0c move.l r1,(r7+rbptr);$10 move.l r1,(r7+rtemp);$14 move.l r1,(r7+tstate);$18 move.l r1,(r7+tptr);$1c move.l r1,(r7+tbptr);$20 move.l r1,(r7+ttemp);$24 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; init page command routine + wait ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; move.l #$29610000,r1 nop move.l r1,(r6+cpcr);init command - page = 01010,code=01011 ; ***wait for command flag to be clear wait2 move.l (r6+cpcr),d1 nop bmtsts #$0001,d1.h; test with cs bit is setted jt wait2 ;if flag is still setted goback to wait nop ;due to restriction 6.4.4.a.3 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; jmp retry nop ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; nak move.l #$a1caaaa,d0 debug bsyerror move.l #$bbbbbbbb,d0 debug ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; end_ nop jmp r3 ;jmp to boot start address endsec
bootloader program functional differences between msc8101 (mask 2k42a) and msc8103 (mask 2k87m), rev. 2 freescale semiconductor 111
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